Clock Jitter Measurement Circuit Using Delayed Clock Sampling
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Solution Overview
Problem
Existing clock signal measurement technologies face challenges in accurately measuring jitter, which affects the performance of digital circuits due to variations in semiconductor manufacturing processes, temperature, and voltage, leading to limited performance and increased design margins.
Innovation Solution
A clock jitter measurement circuit that generates internal and delayed clock signals, latches a single pulse signal synchronized with these signals, and counts active sampling signals to determine jitter, allowing for precise measurement and performance optimization of digital circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If design margins are increased to account for clock jitter variations, then reliability is improved, but device performance is limited
Solution Approach 1:
The patent replaces traditional analog jitter measurement methods with a digital measurement system that uses digital logic circuits (latch circuits, counters, delay units) to measure and characterize clock jitter. This digital approach provides more precise and reliable jitter measurement without requiring excessive design margins, thereby resolving the contradiction between reliability and performance.
Solution Approach 2:
The patent changes the measurement parameter from direct time-domain jitter measurement to a digital count-based measurement system. By converting jitter measurement into counting operations on delayed clock signals, the system achieves high precision and reliability while maintaining circuit performance, as the measurement process itself does not burden the clock signal path.
2Measurement precision
If traditional jitter measurement methods are used, then measurement is simpler, but measurement precision is insufficient
Solution Approach 1:
The patent segments the jitter measurement process into distinct functional modules: delay units that create time-shifted versions of the clock signal, latch circuits that capture signal states, and counters that tally the captured states. This segmentation allows each component to perform a specific function with high precision, achieving accurate jitter measurement while keeping individual components relatively simple.
Solution Approach 2:
The patent introduces delay units as intermediary components that create multiple time-shifted copies of the clock signal. These delayed signals serve as mediators between the original clock signal and the measurement logic, enabling precise jitter characterization without directly burdening the primary clock path, thus improving measurement precision while managing circuit complexity.
3Reliability
If measurement circuits are added to characterize jitter, then jitter impact is reduced, but device complexity increases
Solution Approach 1:
The patent replaces complex analog jitter compensation circuits with a digital measurement and characterization system. By using digital logic elements (latches, counters, delay units) to measure and characterize jitter, the system achieves improved jitter tolerance through accurate measurement and potential feedback control, while avoiding the complexity and instability of analog compensation circuits.
Data Source
AI summary
A circuit for measuring clock jitter includes: an internal signal generator configured to generate an internal clock signal and a single pulse signal, respectively synchronized with an input clock signal; a plurality of delay units being connected in series with each other and configured to generate respective delayed clock signals; a plurality of latch circuits configured to latch the single pulse signal in synchronization with the respective delayed clock signals, and output sampling signals; and a count sub-circuit configured to output a count value resulting from counting a number of active sampling signals of the sampling signals.