Digital Circuit Testing TRIZ Cases

Flip-flop shift registers replace SRAM configuration cells in an FPGA to cut area, simplify testing, and lower power with selective clocking.

Internal test signal paths let directly attached memory controllers measure setup and hold timing when external pins are inaccessible.

A calibration circuit detects metastability and shifts PLL phase to align clocks across different frequencies without separate PLLs or dividers.

A synchronized counter and phase-difference combiner improve reciprocal count accuracy by avoiding multi-phase clock skew.

Shared clock-gated supply transistors cut scan flip-flop clock-tree load and dynamic power without sacrificing switching performance.

A programmable on-chip counter triggers repeated captures during PLL startup, enabling accurate lock-time and frequency-transition validation.

A unified PSoC array combines reconfigurable analog and digital blocks to cut chip area and avoid multi-chip communication overhead.

An integrated asynchronous clock test circuit measures timing margin inside each processor, avoiding connector errors and covering real conditions.

Using selectable delay units and count-based control, this clock circuit generates multiplied or divided clocks with short locking time and low area.

Automatic error detection switches clock output to a backup oscillator, improving reliability without adding separate comparison hardware.

Local satellite ADCs calibrate voltage references and send digital monitor data over a NoC, avoiding heavy analog routing in programmable devices.

Logic-level conversion enables short detection at CS and CKE terminals in multi-chip memory packages by comparing written and read signals.

A variable resistor tunes the probe RC time constant to stabilize attenuation across frequencies without bulky, drift-prone variable capacitors.

Independent die-region power networks and stitched metal lines cut wafer-test power while enabling loopback checks and faulty-region isolation.

Integrating phase-difference timing with edge counting improves frequency count accuracy while avoiding clock skew from parallel modulators.

A differential RC path and Schmitt-trigger fault flag let LVDS lines be monitored accurately at high frequency without receiver dependence.

A configurable stimulus-response controller analyzes MTJ waveforms locally to cut handshaking delays and speed electrical characterization.

Buffer memory and FIFO control let a logic block recover from radiation-induced transient errors without interrupting execution rhythm.

By integrating LSSD scan into multi-bit sequential cells and sharing clock inverters, this case cuts area, pin density, and power.

A dual-monitor scheme tracks supply voltage and critical path delay to detect lowest operating voltage despite aging-related accuracy drift.

An on-die digital circuit uses a free-running oscillator to measure clock delay accurately without external equipment or PVT compensation.

Secondary clock shifts cancel programmable multiplexer delay, improving critical path monitoring accuracy and aging margin compensation.

Buffer-backed input replay lets a digital logic circuit recover from radiation-induced transient errors without slowing processing or adding heavy redundancy.

Critical loads on violating nets are reassigned to opposite-edge flip-flops to fix hold timing without extra wirelength or routing congestion.

An inverter and MUX let existing LBIST generate original and inverted scan patterns for deterministic SRPG flip-flop state retention testing.

Tapped transmission lines and transimpedance amplifiers help deliver high-speed clocks over distance with lower insertion loss and multi-point reception.

Using one scan input and linked scan paths, this multi-bit flip-flop layout reduces pin count, circuit complexity, and power while keeping testability.

A reconfigurable PSoC combines programmable analog and digital blocks on one chip, cutting area and cost while enabling on-the-fly debugging.

A hardware trigger and control circuit switches transmission paths without software, improving mode reliability and easing fault isolation.

PLL and frequency divider circuitry create a wide-range test clock for faster, flexible on-chip speed grading of logic cores.

Selective transistor shorts flip master or slave scan latches, exposing faulty stages through alternating versus constant output patterns.

Flip-flop shift registers replace SRAM-based FPGA configuration to cut chip area, simplify testing, and support error detection.

Mode signal circuits compare transistor current-dependent timing with passive elements to identify MOS variation and cut power use.

Post-fabrication ring oscillator signals estimate real cell delays, improving IC simulation accuracy under manufacturing variation.

Internal test signal paths delay clock and data edges to measure setup and hold timing in directly attached 3D-ICs with inaccessible pins.

Mode-switched tristate inverter paths shift master and slave clock timing to cut scan hold time, power use, and flip-flop area.

A programmable scan chain reuses FPGA resources to speed debug read-back and emulation without intrusive ILA overhead.

An integrated PLL and logic circuit injects clock jitter internally to measure timing margin per unit without connector-induced errors.

Terminal checkers compare pad configurations with allowed states and force defaults to prevent unsafe multiplexed I/O errors.

A fixed scan bit propagates through internal latches to initialize multi-bit flip-flops without extra set/reset circuitry, saving area and power.

A two-stage on-chip delay scheme improves jitter window estimation by combining coarse and fine phase tuning for higher measurement resolution.

Delayed clock signals, latch sampling, and count logic measure input clock jitter precisely without excessive design margins.

A shared comparator with switchable reference levels cuts boundary scan receiver area while supporting accurate AC and DC mode detection.

A PSoC combines UDBs with programmable analog blocks to reconfigure mixed-signal functions on one chip, reducing area and chip count.

On-chip ECC logic generates correct check bits during scan testing, improving defect coverage without complex external pattern generation.