FPGA Shift-Register Configuration for Testable Low-Area Logic
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Solution Overview
Problem
Field Programmable Gate Arrays (FPGAs) face challenges with space efficiency and testability due to the extensive interconnection tracks and memory addressing requirements, which complicate manufacturing and increase power consumption.
Innovation Solution
Implementing a Field Programmable Gate Array with a programming shift register configuration using flip flops instead of SRAM memory cells, allowing for reduced chip area and improved testability through scan chain techniques, and enabling modes for loading test values and logic function implementations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of stationary object
If SRAM memory cells are used for configuration storage, then non-volatile configuration is achieved, but chip area increases and testability deteriorates
Solution Approach 1:
The patent extracts the configuration storage function from traditional SRAM memory cells and implements it using flip-flops integrated into the logic blocks. This removes the need for separate memory addressing circuits and reduces chip area while maintaining configuration retention through the flip-flop state storage capability
Solution Approach 2:
The flip-flops serve dual purposes: they store configuration data and simultaneously function as test elements for scan chain testing. This multi-functionality eliminates the need for separate test structures, reducing overall chip area while improving testability
2Adaptability or versatility
If extensive interconnection tracks are provided, then routing flexibility is improved, but chip area increases and manufacturing complexity worsens
Solution Approach 1:
The patent segments the interconnection structure by providing separate dedicated tracks for configuration data and separate tracks for normal data operation. This segmentation allows efficient routing of configuration information without interfering with operational signals, reducing the total track count needed while maintaining routing flexibility
Solution Approach 2:
The patent introduces scan chain flip-flops as intermediary elements that mediate between the configuration input and the logic block configuration. These flip-flops buffer and transfer configuration data through a structured path, reducing the need for direct extensive interconnection tracks while maintaining configuration flexibility
3Manufacturing precision
If memory addressing circuits are added, then configuration precision is improved, but device complexity increases and power consumption worsens
Solution Approach 1:
The patent extracts the addressing function from separate memory addressing circuits and integrates it into the scan chain structure. The scan chain itself provides the sequential addressing mechanism through its shift register operation, eliminating the need for complex separate addressing logic while maintaining precise configuration delivery
Solution Approach 2:
The scan chain flip-flops self-address through their inherent shift register operation. Each flip-flop is automatically addressed in sequence through the scan chain loading process, eliminating the need for external addressing circuits while maintaining precise configuration delivery to the correct logic blocks
4Difficulty of detecting and measuring
If scan chain testing is implemented, then testability is improved, but additional flip flops are required increasing chip area
Solution Approach 1:
The patent makes the configuration flip-flops serve dual purposes: they store configuration data during normal operation and simultaneously form the scan chain for testing. This multi-functionality provides complete test coverage without requiring additional dedicated test flip-flops, avoiding extra chip area while maximizing testability
Data Source
AI summary
Configuration values for Lookup tables (LUTs) and programmable routing switches in an FPGA are provided by means of a number of flip flops arranges in a shift register. This shift register may receive test values in a factory test mode, and operational configuration values (implementing whatever functionality the client requires of the FPGA) in an operational mode. The bitstreams are provided at one end of the shift register, and clocked through until the last flip flop receives its value. Values may also be clocked out at the other end of the shift register to be compared to the initial bitstream in order to identify corruption of stored values e.g. due to radiation exposure. A clock gating architecture is proposed for loading data to or reading data from specific selected shift registers.