FPGA Scan Chain Circuit for High-Speed Non-Intrusive Debugging
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Solution Overview
Problem
Current debugging methods for FPGAs, such as in-system debug and prototype/emulation, are inefficient and intrusive, limiting effective emulation speed due to the need for extensive resource usage and slow read-back mechanisms.
Innovation Solution
A circuit and method for implementing a high-speed scan chain in programmable resources of an integrated circuit, utilizing programmable elements, selection circuits, and registers to create a non-intrusive and fast scan chain without additional placement or routing resources, enabling efficient emulation and manufacturing verification testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If prototype/emulation is performed by monitoring 100 percent of design running on FPGA using ILA, then measurement precision is improved, but device complexity and area consumption increase significantly
Solution Approach 1:
The patent extracts the debugging function from the complex ILA infrastructure and implements it using the existing scan chain infrastructure. By reusing the scan chain that already exists for configuration and testing purposes, the design achieves 100% debugging coverage without adding ILA resources or increasing device complexity.
Solution Approach 2:
The scan chain is made multi-functional by using it for both its original purposes (configuration, boundary scan) and for debugging/prototyping. This universal approach allows the same hardware infrastructure to serve multiple functions, eliminating the need for separate ILA resources while achieving comprehensive signal monitoring.
2Reliability
If prototype/emulation is performed by advancing clock one cycle and performing chip read-back using configuration network, then debugging capability is improved, but productivity decreases due to slow effective emulation speed
Solution Approach 1:
The patent introduces a dedicated scan output path as an intermediary between the internal logic and the external debug interface. This separate path allows data to be read out through the fast scan chain infrastructure rather than through the slower configuration network, dramatically improving emulation speed while maintaining debugging capability.
Solution Approach 2:
The patent replaces the mechanical/configuration-based read-back mechanism with a digital scan-based output mechanism. Instead of using the configuration network (designed for slow, sequential configuration), the system uses the scan chain (designed for fast, synchronous data movement) to read out debug data, achieving kHz-MHz emulation speeds.
3Ease of operation
If in-system debug is performed using ILA connected to selected signals, then ease of operation is improved for interactive debugging, but manufacturing precision decreases because it cannot be implemented in production without logic predefined
Solution Approach 1:
The patent enables the design to debug itself by using the existing scan chain infrastructure that is already present in the manufactured device. No additional debug logic needs to be predefined or added during manufacturing - the scan chain resources already built into the FPGA fabric are reused for debugging purposes, making the solution both operationally easy and manufacturing-ready.
Data Source
AI summary
A circuit for implementing a scan chain in programmable resources of an integrated circuit is described. The circuit comprises a programmable element configured to receive an input signal and generate an output signal based upon the input signal; a selection circuit configured to receive the output signal generated by the programmable element at a first input and to receive a scan chain input signal at a second input, wherein the selection circuit generates a selected output signal in response to a selection circuit control signal; and a register configured to receive the selected output signal of the selection circuit.