Multi-Bit Vectored Sequential Scan Cells With Shared Clock Inverters
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Solution Overview
Problem
Modern microprocessors and digital integrated circuits face challenges in reducing silicon cost, PCB footprint, and power consumption due to the significant overhead of testability circuits like Level-Sensitive Scan Design (LSSD) in latches and flip-flops, which occupy a large area and consume power.
Innovation Solution
The integration of multi-bit latches and flip-flops with internal connection of scan clocks, inputs, and outputs using local metal, and the use of time-borrowing vectored flip-flops with shared clocking circuitry to reduce area and power, while maintaining performance by optimizing transistor usage and clock pin capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If LSSD testability circuits are added to latches and flip-flops, then test capability is improved, but area overhead increases significantly (consuming approximately 70% of the standard cell size)
Solution Approach 1:
The patent merges the LSSD testability circuits with the standard latch/flip-flop cell to create an integrated structure. The scan logic is combined with the storage elements, allowing test functionality to be embedded within the standard cell footprint rather than added as separate external circuits, thereby reducing the overall area overhead while maintaining test capability
Solution Approach 2:
The patent designs a universal standard cell that performs both normal operational functions (data storage and transfer) and test functions (scan operations) within the same structure. The cell can operate in either normal mode or scan mode depending on control signals, eliminating the need for separate dedicated test circuits and reducing area consumption
2Reliability
If multi-bit latches with LSSD scan are implemented, then testability is improved, but area overhead and power consumption increase
Solution Approach 1:
The patent combines multiple bit-latches into a single multi-bit standard cell with integrated LSSD scan functionality. By merging the scan circuits with the storage elements at the multi-bit level, the patent reduces redundant circuitry and minimizes power consumption while maintaining comprehensive testability across all bits
Solution Approach 2:
The patent recovers and reuses existing circuit resources within the multi-bit latch structure to provide scan functionality. Instead of adding completely separate test circuits, the patent repurposes existing logic paths and storage elements to perform scan operations, thereby reducing additional power overhead while maintaining test capability
Data Source
AI summary
An apparatus is provided which comprises: a multi-bit quad latch with an internally coupled level sensitive scan circuitry; and a combinational logic coupled to an output of the multi-bit quad latch. Another apparatus is provided which comprises: a plurality of sequential logic circuitries; and a clocking circuitry comprising inverters, wherein the clocking circuitry is shared by the plurality of sequential logic circuitries.