Digital Logic Circuit Recovery From Transient Errors Using Buffer Replay
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Solution Overview
Problem
Digital integrated circuits face challenges in protecting against transient errors induced by ionizing radiation without significantly increasing logical complexity or disrupting processing performance, especially in aerospace and complex ground systems.
Innovation Solution
A digital integrated circuit design incorporating a logic assembly with a functional logic block, error detection logic, FIFO memories, and a control logic unit that manages error detection and correction by switching inputs and controlling processing rates to maintain continuous operation without observable impact on execution speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If metallic shielding is used to protect against ionizing radiation, then transient errors are reduced, but space and weight constraints prevent complete protection
Solution Approach 1:
The patent introduces a buffer memory as an intermediary component that stores previous input data. When a transient error is detected in the functional logic block, the control logic unit retrieves the correct data from the buffer memory, acting as a mediator to restore proper operation without requiring heavy shielding
Solution Approach 2:
The buffer memory creates a copy of the input data before it enters the functional logic block. This copy serves as a backup that can be used to restore correct operation when errors occur, providing protection without adding physical shielding mass
2Reliability
If silicon-on-insulator technology is used, then transient errors are reduced, but manufacturing costs increase
Solution Approach 1:
The patent segments the protection mechanism into separate functional components: error detection logic, control logic unit, and buffer memory. This allows protection to be implemented as a modular add-on to existing standard-silicon circuits, avoiding the need for expensive silicon-on-insulator manufacturing while maintaining reliability benefits
3Reliability
If logic gates are designed with higher redundancy and capacitance, then transient error resistance improves, but execution speed decreases
Solution Approach 1:
The buffer memory pre-stores input data before it enters the functional logic block. When errors occur, the control logic unit can immediately retrieve correct data from the buffer without waiting for slow redundant logic operations, thus maintaining high execution speed while providing error protection
Solution Approach 2:
The patent replaces the mechanical approach of adding redundant logic gates and increasing capacitance with an information-based approach using buffer memory and error detection logic. This substitution maintains execution speed while achieving transient error resistance through data backup and verification rather than through slower physical logic structures
4Reliability
If modular triplication and majority voting is implemented, then error correction capability improves, but logical complexity and power dissipation increase significantly
Solution Approach 1:
Instead of creating three complete copies of the functional logic block as in TMR, the patent creates a single copy in the buffer memory of just the input data. The error detection logic then verifies results against this copy, dramatically reducing logical complexity while maintaining error correction capability
Solution Approach 2:
The patent extracts only the essential protective function (data backup and verification) from the complex TMR framework. By separating error detection into a dedicated logic unit and using a simple buffer memory for data copying, the solution achieves error correction with minimal added complexity compared to full TMR implementation
5Productivity
If buffer memory is used to store previous inputs, then service continuity is maintained, but device complexity increases
Solution Approach 1:
The buffer memory serves multiple functions: it acts as a data backup for error correction, a buffer for data flow management, and a source for retrieving correct data when errors occur. This multi-functionality justifies the added complexity by providing service continuity through a single versatile component rather than multiple specialized components
Data Source
Figure 1~2b
Figure 2c
Figure 3a~3b
AI summary
A digital integrated circuit comprising a logic assembly (120) including a functional logic block (101), a logic unit (102) for detecting transient errors impacting the functional logic block (101), an input FIFO memory (103) for supplying samples to the functional logic block (101), an output FIFO memory (104) for receiving samples from the output of the functional logic block (101), a buffer memory (105) supplied with samples by the input FIFO memory (103), and a control logic unit (106) capable of controlling read access to the input FIFO memory (103) and write access to the output FIFO memory (104) and configured to, when an error is detected by the transient error detection logic unit (102), reset the transient error detection logic unit (102) and the functional logic block (101),suspend write access to the output FIFO memory (104) and switch the input of the functional logic block (101) to the output of the buffer memory (105).