Scan Latch Flip Circuit for Fault Isolation in Debug Chains
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Solution Overview
Problem
Debugging chains of conventional scan-only latches is challenging due to the serial scanning process, where downstream latches are initialized with values from a failing latch, making it difficult to determine which latch is faulty, especially when latches power-up in consistent states or random, repeatable states.
Innovation Solution
Incorporating a device, such as a transistor, to selectively short-circuit the latch circuit and flip the latch state, allowing the identification of faulty latches by observing alternating output patterns when the flip control is activated, reducing overhead to as few as two transistors per master-slave latch pair.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional scan-only latches are used with serial scanning process, then the latch circuit structure is simple, but it becomes very difficult to debug when a latch fails because downstream latches are initialized with the stuck value
Solution Approach 1:
The patent applies preliminary action by pre-configuring flip devices (transistors) within the latch circuit that can be activated before debugging operations. These devices are prepared in advance to force specific latch states (0 or 1) when needed, allowing debuggers to initialize downstream latches with known values before scanning, thereby enabling effective fault detection without modifying the basic latch structure.
2Difficulty of detecting and measuring
If logic gates or multiplexors are added to debug the latch chain, then fault detection capability is improved, but the device complexity and cost increase significantly
Solution Approach 1:
The patent merges the debugging functionality directly into the existing latch circuit structure by integrating flip devices (transistors) within the latch itself. Instead of adding separate logic gates or multiplexors as external debugging components, the solution combines fault detection capabilities with the latch's core structure, thereby improving fault detection while minimizing additional circuit complexity.
Solution Approach 2:
The latch circuit provides its own debugging capability through integrated flip devices that can force latch states. This self-service approach eliminates the need for external debugging infrastructure like XOR gates or multiplexors, as the latch circuit itself contains the necessary mechanisms to initialize and test its own state, reducing overall system complexity.
3Productivity
If a device is added to selectively short circuit and flip latch state, then fault detection efficiency is improved, but the transistor count per latch increases
Solution Approach 1:
The patent applies local quality by adding flip devices (typically one or two transistors) only to specific critical points within the latch circuit where state forcing is needed, rather than duplicating full debugging infrastructure in every latch. This localized approach enables efficient fault detection across the entire chain while minimizing the total transistor count increase, as each latch adds only the necessary minimal components.
Data Source
AI summary
A latch circuit having a master latch and a slave latch includes a device used to short either the master latch or the slave latch. The device includes a transistor and a global control used to assert a signal, and is positioned to short an inverter of the master latch or the slave latch. When the signal is asserted by the global control, the inverter is shorted such that the output value of the inverter is the same as the input value. The assertion of the signal is facilitated by another device connected to the master latch and the slave latch that includes the global control and a transistor.