Count Value Generation Circuit for Clock Skew-Free Frequency Measurement
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Solution Overview
Problem
Count value generation circuits using frequency delta sigma modulators face accuracy issues due to clock skew caused by using signals with different phases as operation clocks, making it difficult to improve the accuracy of count values.
Innovation Solution
A count value generation circuit that includes a first counter for counting reference signal edges, a time digital value generator to calculate phase differences, and a count integrated value combiner to produce a count value based on the difference between integer multiples of the count value and time digital value, improving accuracy by eliminating the need for signals with different phases.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a count type frequency counter uses a plurality of FDSMs coupled in parallel to perform frequency delta sigma modulation, then the frequency measurement capability is improved, but clock skew increases and measurement precision deteriorates
Solution Approach 1:
The patent inverts the conventional approach by using a single FDSM instead of multiple parallel FDSMs. The counter measures the frequency of the reference signal while using the input signal as the clock source, rather than using multiple signals with different phases. This inversion eliminates clock skew between multiple clocks while maintaining frequency measurement capability.
Solution Approach 2:
The patent extracts and eliminates the problematic element of using multiple signals with different phases. By using only a single FDSM with the input signal as clock source, the patent removes the source of clock skew while preserving the essential frequency measurement function through a different operational approach.
2Productivity
If multiple signals with different phases are used as operation clocks in parallel FDSMs, then frequency measurement function is enhanced, but device complexity increases
Solution Approach 1:
The patent removes the complex multi-signal, multi-FDSM architecture and extracts only the essential frequency measurement function. By using a single FDSM with the input signal as clock source, the device complexity is reduced while maintaining the core measurement capability.
Solution Approach 2:
The input signal serves multiple functions: it acts as the clock source for the FDSM and simultaneously as the signal whose frequency characteristics are being measured. This multi-functionality reduces the need for separate signal paths and reduces overall device complexity.
Data Source
AI summary
A count value generation circuit includes a first counter that counts edges of a reference signal to generate a first count value in synchronization with an input signal, a time digital value generator that generates a time digital value corresponding to a phase difference between the reference signal and the input signal, a count integrated value combiner that outputs a difference between an integer multiple of the first count value and the time digital value, and a count value generator that generates a count value based on a difference between a first output value and a second output value output from the count integrated value combiner.