On-Chip ECC Scan Path Testing With Correct Check Bit Generation
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Solution Overview
Problem
Testing integrated circuits with error checking and correcting (ECC) protected logic is challenging due to the difficulty in generating correct ECC check bit patterns, as random pattern testing often results in incorrect check bits, which can lead to incomplete defect detection.
Innovation Solution
A method that initializes scan paths on integrated circuits using on-chip ECC generation logic to generate correct ECC check bits, allowing for thorough testing of ECC protected logic and downstream logic, and includes additional clock cycles to update check bits during the scan process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If random pattern testing is used to test ECC protected logic, then testing can be performed with simple test generation, but the check bits will be incorrect most of the time resulting in poor defect detection
Solution Approach 1:
The test system uses on-chip ECC generation logic to automatically generate correct check bits during the test process. The chip's own ECC circuitry serves the dual purpose of both protecting data and generating valid test patterns, eliminating the need for external test pattern generation while ensuring correct check bits are always produced
Solution Approach 2:
The on-chip ECC generation logic is utilized for both its primary function (protecting data during normal operation) and secondary function (generating correct check bits for testing). This multi-functional use of existing circuitry resolves the contradiction by providing reliable defect detection capability without requiring separate test generation equipment
2Reliability
If thorough testing of ECC protected logic is performed with correct check bits, then defect detection capability is improved, but test time and complexity increase
Solution Approach 1:
The system pre-loads correct check bits into latches before the actual test execution begins. By preparing the correct check bit patterns in advance using the on-chip ECC logic, the system ensures that during test execution, the correct patterns are already available, eliminating the need for time-consuming check bit generation during the test itself
Solution Approach 2:
The test system continuously loads new values into scan channels from the PRPG while simultaneously unloading responses into the MISR. This continuous operation, combined with the pre-loaded correct check bits, maintains high test throughput while ensuring defect detection capability is not compromised
3Productivity
If LBIST is used to test all logic including ECC logic, then tester time and memory usage are reduced, but correct check bit patterns are difficult to generate
Solution Approach 1:
The LBIST system leverages the chip's own on-chip ECC generation logic to produce correct check bits. Instead of requiring complex external test equipment to generate valid ECC patterns, the device under test uses its inherent ECC circuitry to generate the necessary test patterns, maintaining high productivity while reducing device complexity requirements
Solution Approach 2:
The on-chip ECC generation logic acts as an intermediary between the PRPG and the scan channels. It takes random patterns from the PRPG and transforms them into valid ECC-protected patterns by generating the correct check bits, thereby enabling LBIST to efficiently test ECC logic without requiring complex external pattern generation
Data Source
AI summary
Aspects include techniques for implementing a clock path technique for using on-chip circuitry to generate a correct encode pattern to test the on-chip circuitry for encoding and correction of a chip. A computer-implemented method may include initializing a scan of the chip including data and a set of check bits protecting the data; applying a global control bit to a latch on the chip; and applying an additional clock to the latch so the check bits are updated using the on-chip circuitry.