Clock Generation Circuit with Delay Units for Short Locking Time
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Solution Overview
Problem
Current semiconductor testers struggle to keep pace with the increasing operation speed of semiconductor devices, as they often cannot generate signals above 200 MHz, necessitating the use of frequency multiplying circuits like DLL or PLL, which require a wide area, long locking times, and complex implementations.
Innovation Solution
A clock generation circuit that includes a frequency detector, control signal generator, and period controller, using a series of unit delayers to generate an internal clock and output clock based on a target frequency, allowing for efficient high-speed testing with a simple structure and short locking time, functioning as both a frequency multiplying and dividing circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If DLL or PLL circuit is used for frequency multiplication, then stable operation and duty ratio compensation are achieved, but circuit area increases and locking time extends
Solution Approach 1:
The circuit is divided into functional modules: delay element units that can be selectively activated, a lock detection unit, and a control unit. This segmentation allows the circuit to achieve frequency multiplication with reduced area by only activating necessary delay elements rather than using a complete DLL/PLL structure.
Solution Approach 2:
The circuit dynamically adjusts the number of activated delay element units based on the locking status. During frequency multiplication, more units are activated; during lock detection, fewer units are activated. This dynamic configuration optimizes both area usage and functional performance.
2Reliability
If DLL or PLL circuit is used for frequency multiplication, then stable operation is achieved, but locking time increases
Solution Approach 1:
The control unit pre-configures the delay element units based on the target frequency multiplication ratio before actual operation begins. This preliminary configuration eliminates the need for iterative adjustment during locking, significantly reducing locking time while maintaining stable operation.
Solution Approach 2:
The lock detection unit provides real-time feedback on the locking status to the control unit, which adjusts the activation of delay element units accordingly. This feedback mechanism ensures rapid convergence to the locked state while maintaining stable operation once locked.
3Productivity
If frequency multiplying circuit is implemented, then high-speed testing capability is achieved, but device complexity increases
Solution Approach 1:
The same delay element units are used for both frequency multiplication and duty ratio adjustment functions. This multi-functionality reduces overall circuit complexity compared to implementing separate circuits for each function, while still achieving high-speed testing capability.
Solution Approach 2:
The circuit achieves different frequency multiplication ratios by changing the number of activated delay element units rather than using different circuit topologies. This parameter-based approach simplifies the overall circuit design while maintaining the ability to perform high-speed testing at various frequencies.
Data Source
AI summary
A clock generation circuit includes: a frequency detector suitable for generating an internal clock, and generating a counting signal indicating a toggling number of the internal clock during an activation period of an input clock; a control signal generator suitable for generating a plurality of period control signals based on a target signal and the counting signal, the target signal indicating a target frequency of an output clock; and a period controller suitable for generating the output clock based on the period control signals.