Wide-Range Test Clock Generation for On-Chip Speed Grading
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Solution Overview
Problem
The operating speed of multi-core system-on-chip is difficult to determine due to process variation and operating conditions, requiring efficient speed grading methods that can dynamically tune supply voltage and operating speed, but existing methods are time-consuming and lack flexible clock signal generation.
Innovation Solution
A wide-range clock signal generation scheme using phase-locked loop and frequency divider circuitry to generate a wide-range test clock signal for on-chip speed grading, incorporating scan chains and a test controller to conduct structural delay tests, allowing for flexible and efficient speed tuning.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If functional tests are used for speed grading, then measurement precision is improved, but productivity deteriorates due to time-consuming test procedures
Solution Approach 1:
The patent segments the speed grading process into two distinct phases: (1) structural delay testing to establish an initial speed estimate, and (2) functional testing to refine the measurement. This segmentation allows the majority of devices to be quickly screened using structural tests, while only borderline cases require time-consuming functional tests, thereby improving overall productivity without sacrificing measurement precision.
Solution Approach 2:
The patent applies partial functional testing rather than complete functional testing for all devices. By using structural delay tests to obtain an initial speed estimate and only applying functional tests when needed (e.g., for devices near speed boundaries), the system performs partial action that is sufficient for most cases, significantly reducing overall test time while maintaining adequate measurement precision.
2Measurement precision
If clock frequency is changed according to specific search strategy for speed grading, then measurement precision is improved, but device complexity increases due to clock signal generation requirements
Solution Approach 1:
The patent implements a universal clock signal generation system that can operate across multiple frequency ranges using the same hardware infrastructure. The phase-locked loop circuitry and frequency dividers are designed to be reconfigurable, allowing a single set of circuits to generate test clock signals for various speed grading scenarios, thereby reducing overall device complexity while maintaining precise speed determination capability.
Solution Approach 2:
The patent employs dynamic clock signal generation where the test clock frequency is adaptively adjusted based on the device's performance characteristics. The system starts with higher frequencies and dynamically reduces them based on test results, allowing precise speed determination without requiring complex pre-configured clock generation for every possible frequency point.
3Adaptability or versatility
If wide-range clock signal generation is implemented for flexible operating modes, then adaptability is improved, but device complexity increases due to additional circuitry
Solution Approach 1:
The patent implements a nested architecture where multiple frequency dividers are cascaded, with each divider operating at different frequency ranges. The output of one divider feeds into the next, creating a nested structure that efficiently covers a wide frequency range. This nesting approach allows adaptable operating modes while minimizing the total number of circuits required, as each nested level reuses the previous stage's output.
Solution Approach 2:
The patent performs preliminary frequency range selection before detailed speed grading measurements. The system first determines the appropriate frequency range using coarse-grained control signals, then applies fine-grained frequency adjustment within that range. This preliminary action allows the system to configure itself for different operating modes without requiring complex real-time adjustments, thereby improving adaptability while controlling circuitry complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables efficient and flexible speed grading, reducing validation time and supporting various operating modes with accurate results, as demonstrated by simulated speed grading results compared to Design Compiler outputs.
Implementation Method 1
wide-range clock signal generation circuitry comprising phase-locked loop circuitry and frequency divider circuitry
Implementation Method 2
the frequency divider circuitry may comprise a first frequency divider and a second frequency divider, wherein the first phase-locked loop circuit generates a high speed clock signal based on the test clock signal, the first frequency divider generates a preliminary tunable clock signal based on the high speed clock signal and the frequency setting signal
Implementation Method 3
the second phase-locked loop circuit generates a tunable clock signal based on the preliminary tunable clock signal
Implementation Method 4
the second frequency divider generates the wide-range clock signal based on the tunable clock signal and the frequency range selection signal
Data Source
AI summary
An integrated circuit for on-chip speed grading comprises test circuitry comprising scan chains and a test controller; and wide-range clock signal generation circuitry comprising phase-locked loop circuitry and frequency divider circuitry. The wide-range clock signal generation circuitry is configured to generate a wide-range test clock signal for the test circuitry to conduct a structural delay test for on-chip speed grading. The wide-range test clock signal is generated based on a test clock signal associated with the test circuitry, a frequency range selection signal and a frequency setting signal.