Master-Slave Clock Circuit With Mode-Switched Scan Timing
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Solution Overview
Problem
In integrated circuits, the use of a single clock generation circuit for both data and scan inputs can lead to timing errors, resulting in increased energy and area consumption due to the need for hold buffers, especially during scan shift modes.
Innovation Solution
A master-slave clock generation circuit is implemented, where a first tristate inverter generates a master signal based on a clock signal when the scan enable signal is asserted, and a second tristate inverter generates the master signal based on a delayed clock signal when the scan enable signal is deasserted, allowing the master clock signal to have different timing relative to the slave clock signal, reducing the need to hold scan input values and minimizing transistor count.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single clock generation circuit is used for both data and scan inputs, then device complexity is reduced, but timing errors occur leading to increased energy and area consumption
Solution Approach 1:
The patent implements dynamic clock timing by using different clock signals (clk_q for data mode, clk_qd for scan mode) depending on the operational mode. The scan enable signal dynamically selects which clock generation path is active, allowing the system to adapt timing characteristics to the current operational requirements while maintaining a unified clock generation architecture
Solution Approach 2:
The patent applies different clock timing characteristics to different input types (data vs. scan inputs) by providing separate clock signals clk_q and clk_qd with different phase relationships. This allows each input path to receive optimally timed clock signals appropriate for its specific requirements, rather than using a single uniform clock signal for all inputs
2Reliability
If hold buffers are added to prevent timing errors, then reliability is improved, but area and power consumption increase
Solution Approach 1:
The patent dynamically adjusts clock timing based on operational mode to inherently prevent timing errors. By switching between different clock generation paths (data path with clk_q, scan path with clk_qd) based on the scan enable signal, the system maintains reliable timing without requiring additional hold buffers or static timing correction circuits
3Manufacturing precision
If separate data and scan clocks are used, then timing precision is improved, but device complexity increases
Solution Approach 1:
The patent implements a universal clock generation circuit that serves multiple functions through mode-based configuration. The same physical circuit structure generates both data clock signals (clk_q) and scan clock signals (clk_qd) by selectively activating different internal paths based on the scan enable signal, thereby achieving timing precision for both modes without duplicating the entire clock generation architecture
Data Source
AI summary
In various embodiments, a master-slave clock generation circuit may include a first delay circuit, a second delay circuit, a first tristate inverter, and a second tristate inverter. The first delay circuit may delay a clock signal and output a slave clock signal and a delayed clock signal. The first tristate inverter may selectively invert the clock signal based on a scan enable signal. The second tristate inverter may selectively invert the delayed clock signal based on the scan enable signal. The second delay circuit may delay a signal received from the first tristate inverter, the second tristate inverter, or both, and output a master clock signal. As a result, the master-slave clock generation circuit may be configured to output a master clock signal and a slave clock signal having differing sets of relative timing characteristics depending on whether the scan enable signal is asserted.