FPGA Shift-Register Configuration for Testable Low-Area Routing
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Solution Overview
Problem
Field Programmable Gate Arrays (FPGAs) face challenges in efficient use of physical resources due to the significant space required for interconnection tracks and memory addressing, which complicates testing and increases power consumption.
Innovation Solution
Implementing a Field Programmable Gate Array with a programming shift register configuration using flip flops instead of SRAM memory cells, allowing for reduced chip area and improved testability through scan chain techniques, and enabling flexible addressing and clock management to optimize power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If SRAM memory cells are used for configuration storage, then non-volatile configuration is achieved, but chip area and power consumption increase significantly
Solution Approach 1:
The patent extracts the configuration storage function from SRAM memory cells and implements it using flip-flops integrated into the logic blocks. This removes the need for separate SRAM arrays, thereby reducing chip area while maintaining configuration retention through the flip-flop state storage capability
Solution Approach 2:
The flip-flops serve dual purposes: they act as both the configuration storage elements and as part of the logic block functional units. This multi-functionality eliminates the need for dedicated SRAM memory cells, reducing overall chip area while maintaining configuration storage capability
2Adaptability or versatility
If SRAM memory cells with addressing circuits are used, then configuration storage is enabled, but device complexity and power consumption increase
Solution Approach 1:
The patent removes the complex SRAM addressing circuits by replacing SRAM with flip-flops that are directly controlled by configuration signals. This extraction of the addressing layer simplifies the device architecture while maintaining configuration storage adaptability
Solution Approach 2:
The patent introduces a configuration controller as an intermediary that directly manages the flip-flop states without requiring traditional SRAM addressing circuits. This mediator simplifies the interface between configuration data and storage elements, reducing device complexity
3Adaptability or versatility
If traditional FPGA interconnection structures are used, then routing flexibility is achieved, but chip area and power consumption increase
Solution Approach 1:
The patent merges the configuration storage function with the logic block functional units by using flip-flops that serve both purposes. This integration reduces the need for separate interconnection structures and memory cells, thereby reducing chip area while maintaining routing flexibility through the programmable nature of the flip-flop configurations
Data Source
AI summary
Configuration values for Lookup tables (LUTs) and programmable routing switches in an FPGA are provided by means of a number of flip flops arranges in a shift register. This shift register may receive test values in a factory test mode, and operational configuration values (implementing whatever functionality the client requires of the FPGA) in an operational mode. The bitstreams are provided at one end of the shift register, and clocked through until the last flip flop receives its value. Values may also be clocked out at the other end of the shift register to be compared to the initial bitstream in order to identify corruption of stored values e.g. due to radiation exposure. A clock gating architecture is proposed for loading data to or reading data from specific selected shift registers.