Digital Logic Recovery From Radiation-Induced Transient Errors
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Solution Overview
Problem
Digital integrated circuits face challenges in protecting against transient errors caused by ionizing radiation without increasing complexity or power dissipation, and existing solutions either fail to provide complete protection or significantly impact the circuit's performance and execution rhythm.
Innovation Solution
A digital integrated circuit design that includes a functional logic block, a transient-error-detecting unit, FIFO memories, and a logic control unit to manage error detection and correction, allowing for transparent error handling without disrupting service or execution rhythm, using a mechanism that involves error detection, buffer memory for state restoration, and dynamic control of processing rhythm.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If metal shielding is used to limit ionizing radiation interaction, then radiation protection is improved, but bulk and weight increase preventing complete protection
Solution Approach 1:
The patent extracts the protection function from physical shielding and relocates it to the digital logic level. Instead of using heavy metal shields to block radiation, the invention uses logic redundancy (TMR - Triple Modular Redundancy) to detect and correct transient errors caused by radiation, achieving protection without the weight and bulk penalties of physical shielding.
Solution Approach 2:
The patent replaces the mechanical/physical protection system (metal shielding) with a digital/logical protection system. The mechanical approach of blocking radiation with material is substituted by a logical approach of detecting and correcting errors through redundant logic paths, achieving the same reliability goal without physical constraints.
2Reliability
If silicon-on-insulator technology is used, then transient errors are decreased, but manufacturing cost increases and protection is not complete
Solution Approach 1:
The patent uses copying in the form of logic replication (TMR - Triple Modular Redundancy). Three copies of the same logic function are executed in parallel, and a majority voter determines the correct output. This logical copying provides transient error protection without requiring expensive silicon-on-insulator manufacturing processes, achieving protection through architectural redundancy rather than material properties.
3Reliability
If logic gates are designed with intrinsic redundancy, then transient error tolerance is improved, but space occupation increases, power consumption increases, and execution speed decreases
Solution Approach 1:
The patent applies dynamics by making the redundancy activation conditional rather than static. The TMR logic is dynamically activated only when transient errors are detected or suspected, allowing the circuit to operate at full speed during normal conditions while providing enhanced protection when needed. This dynamic approach balances execution speed with error tolerance.
Solution Approach 2:
The patent changes the operational parameters of the logic gates by using dynamic voltage and frequency scaling in conjunction with TMR. The system can adjust its operating parameters based on radiation environment conditions, operating in high-speed mode when protection is less critical and in high-reliability mode with activated redundancy when radiation exposure is elevated, thus optimizing the trade-off between speed and tolerance.
4Reliability
If triple-modular-redundancy technique is implemented, then error correction capability is improved, but logic complexity and power dissipation increase significantly
Solution Approach 1:
The patent segments the protection function into separate modular components: error detection logic, TMR voting logic, and correction logic. This segmentation allows each component to be optimized independently and enables selective activation of protection mechanisms based on system state and radiation conditions, reducing overall logic complexity compared to fully activated TMR.
Solution Approach 2:
The patent creates universal protection logic that can be applied to multiple different logic functions and circuit types. The TMR framework and error detection mechanisms are designed as reusable modules that can protect various subsystems (ALUs, memory interfaces, control logic) without requiring separate protection circuits for each, thereby reducing overall system complexity while maintaining comprehensive error correction capability.
Data Source
AI summary
A digital integrated circuit comprising a logic array comprises a functional logic block, a logic unit for detecting transient errors affecting the functional logic block, an input FIFO memory for supplying the functional logic block with samples, an output FIFO memory for receiving samples output from the functional logic block, a buffer memory that is supplied with samples by the input FIFO memory, and a logic control unit that is able to control read access to the input FIFO memory and write access to the output FIFO memory and that is configured, when an error is detected by the transient-error-detecting logic unit, to reset the transient-error-detecting logic unit and the functional logic block, to suspend write access to the output FIFO memory and to switch the input of the functional logic block to the output of the buffer memory.