On-Chip Jitter Measurement Using Coarse and Fine Delay Circuits
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Solution Overview
Problem
Existing on-chip jitter measurement mechanisms rely solely on delay elements for phase delay, limiting the resolution of jitter measurement and making it difficult to accurately detect the jitter window of a clock signal.
Innovation Solution
An apparatus and method utilizing a combination of first and second delay circuits, along with a control circuit, to impose a coarse phase delay and fine-tune the phase delay using different types of delay elements, allowing for precise estimation of jitter by adjusting the delay differences between these elements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If only delay elements are used to directly impose phase delay for jitter detection, then the measurement mechanism is simple, but the resolution of measurement result is limited and cannot be raised efficiently
Solution Approach 1:
The delay circuit is segmented into multiple delay elements connected in series, where each delay element contributes a portion of the total delay. This segmentation allows the total delay to be divided into multiple controllable segments, enabling finer resolution in jitter measurement by selectively activating different combinations of delay elements.
Solution Approach 2:
The delay circuit incorporates controllable delay elements whose delay amounts can be dynamically adjusted based on control signals. This dynamic capability allows the system to adaptively tune the delay amount to match the jitter window size, thereby improving measurement resolution without requiring a fixed complex circuit structure.
2Measurement precision
If external equipment is used to measure jitter via conducting wires, then the measurement mechanism is simple to implement, but the measured jitter window differs from the actual jitter window due to resistor, inductor and capacitor effects
Solution Approach 1:
A delay circuit is introduced as an intermediary component between the clock signal source and the jitter detection mechanism. This delay circuit compensates for the effects of conducting wires by providing a controllable delay that matches the wire-induced delay, thereby enabling accurate jitter measurement without requiring external equipment.
Solution Approach 2:
The patent replaces the mechanical/physical measurement approach (using external equipment and conducting wires) with an on-chip electronic measurement system. By implementing the delay circuit and jitter detection mechanism directly on the chip, the system eliminates the need for external measurement equipment and conducting wires, thereby achieving both accuracy and ease of manufacture.
Data Source
AI summary
An apparatus for jitter measurement includes a first delay circuit, a second delay circuit, and a control circuit. The first delay circuit imposes a preliminary phase delay on an input signal to generate a delayed input signal. The second delay circuit operates with the first delay circuit to impose a fine phase delay on the delayed input signal. The control circuit controls amounts of delays imposed by the first and second delay circuits, and fine tunes the phase delay of the delayed input signal according to the amounts of delays respectively imposed by delay elements of the first and second delay circuits, and estimates or calculates a jitter window for the input signal according to adjustment results of the first and second delay circuits.