Mixed-Signal Array Reconfiguration for Single-Chip Analog-Digital Integration

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Solution Overview

Problem

Current microcontrollers lack the ability to dynamically program both analog and digital circuits on the same semiconductor chip, requiring pre-programming and necessitating multiple chips for complex communication between analog and digital circuits, which increases area and cost on the chip.

Innovation Solution

A Programmable System-on-Chip (PSoC) architecture that integrates programmable universal digital blocks (UDBs) and mixed-signal SC/CT blocks, allowing for dynamic reconfiguration of digital and analog functions, enabling on-the-fly programming and reducing the need for multiple chips.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If general purpose digital circuits (PLA or FPGA) are used to provide flexibility, then adaptability is improved, but device complexity and chip area increase excessively

Engineering Contradiction:
ImproveprogrammabilityVSAvoiddigital logic amount
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent applies universality by creating a single reconfigurable logic cell that can perform multiple digital logic functions (AND, OR, NAND, NOR, XOR, etc.) through programmable connections. Instead of dedicating separate circuits for each logic function, one universal cell with configurable interconnections replaces many specialized circuits, reducing overall device complexity while maintaining full programmability.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent segments the digital circuit into an array of identical, modular logic cells. Each cell is a standardized building block with fixed internal structure but programmable interconnections. This segmentation allows the complex overall function to be achieved through simple, repeatable units rather than a monolithic complex circuit.

Inventive Principle:
Principle #1Segmentation

2Device complexity

If pre-programming is used to simplify circuit design, then device complexity is reduced, but adaptability deteriorates as dynamic reconfiguration becomes impossible

Engineering Contradiction:
Improveprogramming requirementVSAvoiddynamic reconfiguration capability
Core Design Contradiction:
Device complexityVSAdaptability or versatility

Solution Approach 1:

The patent implements dynamics by making the logic cell interconnections reconfigurable during operation. The programmable switches and routing paths allow the circuit topology to change dynamically based on operational requirements. This enables the same hardware to adapt to different computational tasks without requiring physical reconfiguration or multiple fixed-function chips.

Inventive Principle:
Principle #15Dynamics

3Adaptability or versatility

If multiple semiconductor chips are used to enable complex communication between analog and digital circuits, then adaptability is improved, but chip area and manufacturing cost increase

Engineering Contradiction:
Improveanalog-digital integrationVSAvoidchip area
Core Design Contradiction:
Adaptability or versatilityVSArea of stationary object

Solution Approach 1:

The patent merges analog and digital circuits onto a single semiconductor chip. The reconfigurable logic cells include both digital logic elements and analog components (such as current mirrors, capacitors, and switches) that can be programmed to perform mixed-signal functions. This integration eliminates the need for multiple separate chips and their interconnections, reducing total chip area and manufacturing complexity.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS10345377B2Combined analog architecture and functionality in a mixed-signal array
Publication Date: 2019.07.09 INFINEON TECHNOLOGIES AMERICAS CORP
  • US10345377B2 patent drawing
  • US10345377B2 patent drawing
  • US10345377B2 patent drawing

AI summary

A programmable device comprises a plurality of programmable blocks, a debug interface coupled with the plurality of programmable blocks, a debug interface coupled with the plurality of programmable blocks, and a power manger coupled with the plurality of programmable blocks. The power manager is configured to supply power to a subset of the plurality of programmable blocks during debugging of the subset while maintaining a different subset of the plurality of programmable blocks in a lower power mode.