Embedded PLL Startup Testing With Triggered Frequency Capture
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Solution Overview
Problem
Existing PLL test devices cannot accurately measure the PLL's lock time and frequency transition due to the lack of a zero-point reference for the target frequency, leading to impractical logistical challenges and potential aliasing in digital sampling oscilloscopes, which prevents the rendering of a frequency vs. time curve and validation of the PLL's lock at the target frequency.
Innovation Solution
The implementation of an on-device programmable counter/timer that starts at the PLL's initialization to the target frequency, generating a trigger signal for frequency measurement devices like oscilloscopes or frequency counters, allowing for the recording of the PLL's frequency vs. time characteristic curve by repeating measurements with different time intervals, thereby validating the PLL's lock at any point in time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If existing PLL test devices are used to measure frequency over time, then frequency data can be captured, but accurate measurement of lock time and frequency transition is prevented due to lack of zero-point reference
Solution Approach 1:
The patent embeds a counter/timer unit directly within the PLL device structure. This nested approach allows the counter to be synchronized with the PLL's internal operations, providing an accurate zero-point reference for frequency transition measurement without requiring external testing equipment. The counter is integrated into the existing PLL architecture, sharing resources and reducing overall system complexity.
Solution Approach 2:
The counter/timer unit acts as an intermediary between the PLL circuit and external frequency measurement devices. It generates trigger signals that synchronize external measurements with the PLL's internal state transitions, enabling accurate lock time measurement by providing a reference point that bridges the internal PLL operations and external observation tools.
2Reliability
If digital sampling oscilloscopes are used to capture PLL frequency transitions, then frequency data can be recorded, but aliasing occurs due to impractical logistical challenges in capturing the transition from zero-point
Solution Approach 1:
The counter/timer unit is configured to start counting simultaneously with the PLL frequency transition, establishing a zero-point reference before the transition begins. This preliminary synchronization ensures that the frequency measurement captures the complete transition process from the starting point, preventing aliasing by ensuring the sampling begins at the correct temporal reference point.
3Measurement precision
If multiple captures with different delay counts are performed manually, then frequency vs. time curve can be obtained, but the process is time-consuming and logistically challenging
Solution Approach 1:
The counter/timer unit automatically generates the series of trigger signals with different delay counts without requiring manual intervention. The unit self-manages the multiple capture operations by internally generating delayed trigger signals, which automatically initiate frequency measurements at predetermined time intervals. This self-service capability eliminates the need for manual setup and execution of multiple captures, significantly reducing testing time while maintaining measurement precision.
Data Source
AI summary
Different delay counts are supplied to a counter to perform multiple frequency captures on the output of a phase-locked loop (PLL) device. A PLL frequency set signal is supplied to the counter for each of the multiple captures performed on the PLL device. The set signal causes the PLL device to transition from a relatively lower frequency state to a relatively higher target (lock) frequency state. A different time delay count is begun each time the set signal is detected at an input of the counter, and a trigger signal is output from the counter each time each of the different delay counts is complete. A frequency detector captures the frequency being output by the PLL device each time the trigger signal is received. Such forms a record of the frequency being output by the PLL device for each different time delay count.