Opposite-Edge Flip-Flops for Hold Timing Violations
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Solution Overview
Problem
Conventional techniques for addressing hold timing violations in integrated circuit designs often consume significant resources and cause routing congestion, as they require adding length to paths by using scarce IC resources, which can lead to failure in implementing circuit designs due to routing issues.
Innovation Solution
A method that detects nets with hold timing violations, generates a list of loads, filters out non-critical loads, and inserts flip-flops triggered by opposite clock edges to drive critical loads, thereby optimizing timing without unnecessarily increasing wirelength.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional techniques are used to address hold timing violations by adding path length, then timing violations are corrected, but routing resources are consumed and routing congestion occurs
Solution Approach 1:
The patent changes the clock edge parameter of the flip-flop from the same edge as the start point to the opposite edge. This parameter change allows the signal to be captured on the opposite clock edge, effectively increasing the available time window for signal propagation without adding physical path length, thus resolving hold timing violations without consuming additional routing resources
Solution Approach 2:
The patent utilizes the periodic nature of clock signals by switching to the opposite clock edge for capturing. This periodic action creates an additional time window within each clock cycle that can be used for signal propagation, allowing timing violations to be corrected by utilizing the existing periodic clock structure rather than adding more routing resources
2Reliability
If path length is increased to correct hold timing violations, then timing requirements are met, but wirelength increases
Solution Approach 1:
Instead of changing the physical length of the wire, the patent changes the temporal parameter of signal capture by using the opposite clock edge. This allows the same physical wirelength to satisfy hold timing requirements by extending the effective capture window through parameter modification rather than physical extension
3Reliability
If routing resources are added to fix timing violations, then timing requirements are met, but routing congestion increases
Solution Approach 1:
The patent resolves timing violations by changing the clock edge parameter rather than adding more routing resources. This approach maintains the existing routing structure complexity while achieving timing compliance, thereby avoiding additional routing congestion that would result from adding more wires or routing paths
Data Source
AI summary
Implementing a circuit design may include detecting, using computer hardware, a net of the circuit design with a hold timing violation, generating, using the computer hardware, a list including each load of the net, and filtering, using the computer hardware, the list based on predetermined criteria by, at least in part, removing each load from the list determined to be non-critical with respect to hold timing. Using the computer hardware, the circuit design is modified by inserting a flip-flop in the net to drive each load remaining on the list, clocking the flip-flop with a clock signal of a start point or an end point of a path traversing the net, and triggering the flip-flop with an opposite clock edge compared to the start point or the end point.