Multi-Bit Flip-Flop Scan Initialization Without Set/Reset Gates
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Solution Overview
Problem
Existing multi-bit data flip-flop solutions require additional transistors or control gates for set and reset capabilities, increasing die area and power consumption due to the need for separate set/reset circuitry within master and slave latches for internal scan chain initialization.
Innovation Solution
The proposed multi-bit data flip-flop employs an internal scan chain and multiplexers to initialize flip-flop bits through sequential propagation of a fixed input scan bit, eliminating the need for additional set/reset transistors or gates, and operates independently of input clock signals during initialization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If additional set/reset transistors or gates are included within master and slave latches for initialization, then initialization capability is provided, but die area increases
Solution Approach 1:
The scan chain is designed to serve dual purposes: normal scan operations and initialization operations. By making the scan chain universal, the patent eliminates the need for separate set/reset circuitry, thereby reducing die area while maintaining initialization capability through the same scan infrastructure
Solution Approach 2:
The patent merges the initialization function with the existing scan chain infrastructure. Instead of having separate set/reset transistors or gates, the initialization capability is combined with the scan chain by controlling the mode select signals to put all latches into initialization mode, allowing a single scan bit to initialize all flip-flop bits
2Ease of operation
If additional set/reset transistors or gates are included within master and slave latches for initialization, then initialization capability is provided, but power consumption increases
Solution Approach 1:
The scan chain is designed to serve dual purposes: normal scan operations and initialization operations. By making the scan chain universal, the patent eliminates the need for separate set/reset circuitry, thereby reducing power consumption associated with additional transistors and gates while maintaining initialization capability through the same scan infrastructure
Solution Approach 2:
The patent merges the initialization function with the existing scan chain infrastructure. Instead of having separate set/reset transistors or gates that consume additional power, the initialization capability is combined with the scan chain by controlling the mode select signals to put all latches into initialization mode, allowing a single scan bit to initialize all flip-flop bits without additional power-hungry circuitry
3Ease of operation
If separate set/reset circuitry is used for initialization, then initialization is achieved, but device complexity increases
Solution Approach 1:
The scan chain is designed to serve dual purposes: normal scan operations and initialization operations. By making the scan chain universal and controlling it through mode select signals, the patent eliminates the need for separate set/reset circuitry, thereby reducing device complexity while maintaining initialization functionality
Solution Approach 2:
The patent merges the initialization function with the existing scan chain infrastructure. Instead of having separate set/reset transistors or gates that add to circuit complexity, the initialization capability is combined with the scan chain by using mode select signals to put all latches into initialization mode, allowing a single scan bit to initialize all flip-flop bits
Data Source
AI summary
Multi-bit data flip-flops are disclosed that provide bit initialization through propagation of scan bits. Input multiplexers are configured to select between input data bits and input scan bits based upon mode select signals. Master latches receive and latch outputs from the input multiplexers. Slave latches receive and latch outputs from the master latches and also provide propagated input scan bits to the input multiplexers. A first state for the mode select signals selects the input data bits for a data mode of operation, and a second state for the mode select signals selects the input scan bits for a scan mode of operation. Further, the input multiplexers, master latches, and slave latches are configured to operate in an initialization mode to pass a fixed input scan bit through the multi-bit data flip-flop based upon initialization signals (e.g., set and/or reset signals).