On-Die Digital Delay Measurement for PVT-Stable Clock Characterization
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Solution Overview
Problem
Conventional techniques for measuring time delay between clocks on an integrated circuit (IC) die lack accuracy independent of process, voltage, and temperature (PVT) variations, and require external equipment, making them unsuitable for high-volume or accurate delay measurements.
Innovation Solution
An all-digital delay measurement circuit (DMC) is implemented on the IC die, using a free-running oscillator to generate an asynchronous reference clock and a digital phase detector to count reference clock edges between two clocks, providing a digitized measurement of time delay that is insensitive to PVT effects and does not require external calibration or equipment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If external equipment is used to measure time delay, then measurement capability is provided, but measurement accuracy and repeatability are poor, and test time increases
Solution Approach 1:
The invention extracts the delay measurement functionality from external off-die equipment and implements it directly on the IC die through an all-digital delay measurement circuit. This integration eliminates the need for external measurement equipment and enables accurate, repeatable measurements to be performed in-situ on the chip, thereby reducing test time while improving measurement precision.
Solution Approach 2:
The invention introduces a free-running oscillator as an intermediary reference clock source on the die, which serves as a stable timing reference for the delay measurement. This intermediary element enables accurate time delay measurement between two clocks without requiring external equipment, resolving the contradiction between measurement accuracy and test time efficiency.
2Measurement precision
If on-die delay line reference is used, then measurement is performed on-die, but accuracy is limited by PVT effects on the delay line reference
Solution Approach 1:
The invention changes the reference from an analog delay line to a free-running oscillator generating a reference clock signal. This parameter change from analog to digital domain makes the measurement immune to PVT effects that plague analog delay lines, as digital circuits have much lower sensitivity to process, voltage, and temperature variations.
Solution Approach 2:
The invention substitutes the mechanical/analog delay line reference with a digital free-running oscillator reference. This replacement eliminates the PVT sensitivity inherent in analog delay lines while maintaining on-die measurement capability, thereby improving both accuracy and reliability.
3Measurement precision
If voltage-offset compensated comparators and regulated reference currents are used, then analog delay measurement is achieved, but PVT effects still limit accuracy
Solution Approach 1:
The invention substitutes complex analog components (voltage-offset compensated comparators and regulated reference currents) with simple digital logic circuits. The all-digital delay measurement circuit uses only digital logic elements, eliminating the need for complex analog compensation circuits while achieving higher accuracy and lower PVT sensitivity.
Solution Approach 2:
The invention replaces expensive, complex analog components with inexpensive digital logic elements. The free-running oscillator and digital counters are much simpler and more robust than voltage-offset compensated comparators, reducing device complexity while improving measurement accuracy.
4Measurement precision
If delay line reference is used, then on-die measurement is enabled, but timing resolution is limited by practical circuit timing resolution
Solution Approach 1:
The invention introduces a free-running oscillator as an intermediary reference with high frequency and stable timing. This reference clock enables fine timing resolution in the digital delay measurement without requiring complex analog delay lines, as the high-frequency digital reference provides superior timing granularity.
Data Source
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AI summary
An all-digital delay measurement circuit (DMC) constructed on an integrated circuit (IC) die characterizes clocking circuits such as full phase rotation interpolators, also constructed on the IC die. The on-die all-digital DMC produces a digital output value proportional to the relative delay between two clocks, normalized to the clock period of the two clocks.