SRPG Flip-Flop Testing Using Inverted LBIST Scan Patterns
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Solution Overview
Problem
Existing built-in test (BIT) circuitry, specifically Linear Feedback Shift Register (LFSR) logic, is not capable of performing deterministic state retention testing of State Retention Power Gating (SRPG) flip-flop circuitry, which is crucial for testing SRPG flip-flops in low-power systems-on-chip (SoCs) during manufacturing and in-field testing.
Innovation Solution
The integration of an inverter and a multiplexer at the start of each scan chain allows for the use of existing Logic Built-In Self-Test (LBIST) circuitry to test SRPG flip-flops by switching between the original and inverted test vectors, enabling comprehensive testing of both '1s' and '0s' with minimal modifications to the SoC design or test flow.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If existing LBIST circuitry is used for testing, then cost and complexity are reduced, but deterministic state retention testing capability is lost
Solution Approach 1:
An inverter is introduced as an intermediary component between the PRPG and scan chain. This inverter enables the LBIST circuitry to perform deterministic state retention testing by inverting the test pattern, allowing the existing circuit to achieve testing capabilities it originally lacked without adding complex new circuitry
Solution Approach 2:
The patent uses inversion of the test pattern through the inverter to enable deterministic testing. By inverting the original test vector, the system can test for both '1s' and '0s' states, achieving comprehensive state retention testing using the existing LBIST infrastructure
2Reliability
If scan testing is used for SRPG flip-flops, then deterministic testing is achieved, but test equipment cost and complexity increase
Solution Approach 1:
The LBIST circuitry is designed to serve multiple functions: it performs both conventional built-in self-test and deterministic state retention testing for SRPG flip-flops. By adding the simple inverter component, the existing circuit achieves dual functionality, eliminating the need for separate scan testing equipment
Solution Approach 2:
The circuit uses its own existing LBIST infrastructure to perform comprehensive testing including state retention testing. The inverter enables the LBIST circuitry to generate and process the necessary test patterns internally, making the system self-sufficient for both conventional and SRPG-specific testing without external specialized equipment
3Reliability
If comprehensive testing of SRPG flip-flops is performed, then testing thoroughness is improved, but design modifications increase
Solution Approach 1:
Instead of modifying the entire test infrastructure, the patent applies a localized change by adding an inverter only at the specific point where test patterns are fed into the scan chain. This minimal local modification enables comprehensive SRPG flip-flop testing without requiring changes to other parts of the design
Solution Approach 2:
The inverter provides a simple structural inversion that enables comprehensive testing capability. By inverting the test pattern at a single point, the system achieves thorough testing of both logic states with minimal design modification
Data Source
AI summary
An integrated circuit includes a plurality of state retention power gating (SRPG) flip-flops coupled in a first chain, wherein the first chain has a first scan input and a first scan output; a pseudo random pattern generator (PRPG) configured to generate test patterns in response to seeds; a multiplexer (MUX) coupled between the PRPG and the first scan input and coupled to receive a select signal; and response compression logic coupled to the first scan output and configured to generate a test signature in response to an output pattern provided at the first scan output. The MUX is configured to, when the select signal has a first value, couple a first output of the PRPG to the first scan input, and, when the select signal has a second value, couple an inversion of the first output of the PRPG to the first scan input.