Built-In Clock Margin Testing for Processor Timing Accuracy
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Solution Overview
Problem
Conventional methods for determining processing system timing margins are inadequate as they fail to account for unique error sources in individual units and introduce additional timing errors through connectors, while laboratory tests are limited to specific conditions, neglecting environmental factors like temperature changes.
Innovation Solution
A built-in test circuit integrated into the processing system, comprising a second asynchronous clock signal generated by a programmable PLL device, which is processed with the main clock signal to determine system timing margin, allowing for testing under various conditions without external connectors and accounting for environmental factors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional laboratory testing methods are used to determine timing margins, then timing margin measurement can be performed, but additional timing errors are introduced through connectors and external testing equipment
Solution Approach 1:
The invention extracts the timing margin testing functionality from external laboratory equipment and integrates it directly into the processing system itself through built-in test circuits. This eliminates the need for external connectors and testing equipment that introduce timing errors, allowing measurements to be performed internally without the harmful external influences.
Solution Approach 2:
The processing system performs its own timing margin testing through integrated built-in test circuits that generate test signals and measure timing margins internally. The system serves itself by using its own resources (clock circuits, logic circuits) to conduct the measurements without requiring external testing equipment, thereby eliminating connector-induced errors.
2Measurement precision
If single production unit testing is performed in laboratory conditions, then timing margin can be determined for a sample unit, but the results do not account for unique error sources in individual units or environmental variations
Solution Approach 1:
Each individual processing unit is equipped with built-in test circuits that enable it to perform its own timing margin measurements. This allows every unit to be tested individually with its unique error sources and characteristics, rather than relying on representative sample testing. The self-service capability ensures that each unit's specific timing margin is accurately determined.
Solution Approach 2:
The testing system is designed to dynamically adapt to different operating conditions by incorporating environmental sensors and adjustable test parameters. The built-in test circuits can modify testing conditions to account for temperature variations and other environmental factors, making the measurement process versatile and applicable to individual units under varying operational conditions.
3Productivity
If laboratory testing is performed under fixed conditions, then timing margin measurement can be completed, but the results do not reflect performance under varying environmental conditions such as temperature changes
Solution Approach 1:
The built-in test system incorporates dynamic environmental sensing and adaptive testing capabilities. Environmental sensors monitor temperature and other conditions in real-time, and the test circuits automatically adjust parameters to account for environmental variations. This allows the system to maintain high productivity while simultaneously covering a wide range of environmental conditions, as measurements can be taken continuously under actual operating conditions rather than requiring separate controlled laboratory environments.
Data Source
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AI summary
A built-in test circuit for testing a system timing margin of a processing device under-test is provided. The processing device includes a controller and first clock circuit, wherein the first clock circuit generates a first clock signal and the first clock signal is a main clock signal provided for operation of the processing device. The built-in test circuit includes a second clock circuit and a logic circuit, both of which are integrated with the processing device. The second clock circuit generates a second clock signal. The logic circuit processes the first and second clock signals and outputs a third clock signal. The third clock signal is used to determine system timing margin of the processing device.