Mixed-Signal Array Architecture for Dynamic Analog-Digital Reconfiguration
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Solution Overview
Problem
Current microcontrollers lack the ability to dynamically program both analog and digital circuits on the same semiconductor chip, requiring pre-programming and necessitating multiple chips for complex circuit interactions, which increases area and cost due to excessive digital logic requirements.
Innovation Solution
A Programmable System-on-Chip (PSoC) architecture that integrates programmable universal digital blocks (UDBs) and mixed-signal SC/CT blocks, allowing for dynamic reconfiguration of both analog and digital circuits, enabling flexible and efficient mapping of functions onto an array without the need for separate chips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If general purpose digital circuits (PLA or FPGA) are used to provide generality, then adaptability is improved, but device complexity and area increase due to excessive digital logic requirements
Solution Approach 1:
The patent implements a universal digital block (UDB) that can be dynamically reconfigured to perform multiple digital functions. Each UDB contains programmable logic elements that can be programmed at compile time and dynamically reprogrammed at runtime to implement different combinational and sequential logic functions, replacing the need for multiple dedicated digital circuits and reducing overall device complexity while maintaining high adaptability
Solution Approach 2:
The patent introduces dynamic reconfiguration capability where the digital circuit logic can be changed during runtime through loading new configuration data into the UDBs. This dynamic aspect allows the same physical hardware to adapt to different computational requirements without requiring excessive static logic resources, thereby reducing device complexity while preserving versatility
2Ease of operation
If pre-programming is used to simplify circuit configuration, then ease of operation is improved, but adaptability deteriorates as circuits cannot be dynamically programmed
Solution Approach 1:
The patent employs compile-time programming where the desired circuit functionality is specified in high-level C code and automatically translated into configuration data for the UDBs and analog blocks. This preliminary action simplifies the designer's workflow while the generated configuration enables the hardware to be dynamically reprogrammed at runtime, thus maintaining both ease of operation and adaptability
Solution Approach 2:
The patent introduces a programming interface and configuration mechanism that acts as an intermediary between the user's high-level specifications and the underlying hardware configuration. This intermediary automatically generates the necessary configuration data and manages the programming process, making the system easy to operate while enabling dynamic reconfiguration capabilities
3Reliability
If separate semiconductor chips are used for analog and digital circuits, then reliability is improved by avoiding excessive digital logic, but device complexity increases and area is wasted
Solution Approach 1:
The patent merges analog and digital circuits into a single integrated architecture on the same semiconductor chip. The universal digital blocks and programmable analog blocks are interconnected through a unified routing infrastructure, allowing complex interactions between analog and digital circuits to be implemented on-chip without requiring multiple separate chips, thereby reducing overall system complexity while maintaining reliability
Solution Approach 2:
The patent creates a universal mixed-signal platform where both analog and digital functions can be implemented using reconfigurable blocks. This universality allows the same chip to handle diverse analog-digital interaction scenarios without requiring dedicated hardware for each case, reducing device complexity while preserving reliability through integrated design
Data Source
AI summary
A programmable device comprises a plurality of programmable blocks, a debug interface coupled with the plurality of programmable blocks, and a power manager coupled with the plurality of programmable blocks. The power manager is configured to supply power to a subset of the plurality of programmable blocks during debugging of the subset while maintaining a different subset of the plurality of programmable blocks in a lower power mode.