Memory Controller Test Circuitry for Pin-Inaccessible Timing Tests
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Solution Overview
Problem
Integrated circuit (IC) devices in directly attached configurations, such as 3D-ICs, pose challenges in testing input and output timing parameters due to inaccessible pins, making it difficult to ensure proper operation, especially when directly attached to another IC device.
Innovation Solution
Incorporating an internal test signal generator and test signal wires that allow for precise adjustment of clock and data signals, enabling the measurement of timing parameters like setup and hold times without impacting global clock signals, thereby facilitating testing of IC devices in directly attached configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If IC devices are directly attached in 3D-IC configuration, then integration density and signal speed are improved, but accessibility of pins for testing deteriorates
Solution Approach 1:
The patent introduces test signal wires as intermediary elements that run alongside the data signal wires between the memory controller and memory device. These dedicated test signal wires provide a pathway for test equipment to access and manipulate timing signals internally, bypassing the need to access external pins of directly attached IC devices. This mediator approach resolves the contradiction by enabling testing through internal routing while maintaining the direct attach configuration for normal operation.
Solution Approach 2:
The patent segments the signaling function by separating data signal wires from test signal wires. The data signal wires handle normal memory operations, while the test signal wires are dedicated exclusively to testing functions. This segmentation allows independent access to timing parameters through test signal wires without interfering with the direct attach configuration, thus resolving the accessibility issue while maintaining integration density.
2Measurement precision
If test equipment accesses input and output pins of IC devices, then timing parameters can be measured, but device configuration complexity increases
Solution Approach 1:
The patent merges the testing function into the existing memory system by integrating test signal generator circuits within the memory controller and memory device themselves. Rather than requiring external test equipment to access pins, the testing capability is combined with the operational circuits, allowing timing parameter measurement through internal test signal wires without adding external complexity to the device configuration.
Solution Approach 2:
The memory system performs self-testing through integrated test signal generators that can internally generate and route test signals through the data path. This self-service capability allows the system to measure its own timing parameters without requiring external test equipment or complex external configurations, thereby maintaining simple device configuration while achieving precise measurement.
3Measurement precision
If test signals are injected into data signal wires, then timing measurement is enabled, but normal data transmission is disrupted
Solution Approach 1:
The patent segments the signaling function by separating data signal wires from test signal wires. The data signal wires handle normal memory operations, while the test signal wires are dedicated exclusively to testing functions. This segmentation allows independent access to timing parameters through test signal wires without interfering with the direct attach configuration, thus resolving the accessibility issue while maintaining integration density.
Solution Approach 2:
The patent introduces test signal wires as intermediary elements that run alongside the data signal wires between the memory controller and memory device. These dedicated test signal wires provide a pathway for test equipment to access and manipulate timing signals internally, bypassing the need to access external pins of directly attached IC devices. This mediator approach resolves the contradiction by enabling testing through internal routing while maintaining the direct attach configuration for normal operation.
Data Source
AI summary
A memory controller instantiated on a semiconductor IC device comprises a timing circuit to transfer a timing signal, the timing circuit being configured to receive a first test signal and to effect a delay in the timing signal in response to the first test signal, the first test signal including a first timing event. The memory controller further comprises an interface circuit configured to transfer the data signal in response to the timing signal, the interface circuit being further configured to receive a second test signal and to effect a delay in the data signal in response to the second test signal, the second test signal including a second timing event that is related to the first timing event according to a test criterion.