Clock Phase Alignment Using Metastability Feedback
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Solution Overview
Problem
Communication systems and processor-based systems face challenges in dynamically aligning clocks with different frequencies, as existing methods require separate phase locked loops (PLLs) and dividers, leading to increased complexity and limited frequency step sizes.
Innovation Solution
A calibration circuit and phase shifter system that uses a comparison flip flop to detect metastability and adjust phase shifts, allowing for clock synchronization without dividers, by generating one clock from another and dynamically aligning variable and reference clocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If separate phase locked loops (PLLs) are used to generate variable clock and fixed clock, then clock frequency flexibility is improved, but device complexity increases
Solution Approach 1:
The patent merges multiple PLL functions into a single PLL by using a calibration circuit that can dynamically adjust phase alignment between different clock outputs. The calibration circuit compares phases of variable clock and fixed clock and generates correction signals to align them, allowing one PLL to serve multiple clock generation purposes that traditionally required separate PLLs.
2Measurement precision
If dividers are used in clock alignment, then frequency synchronization is improved, but device complexity and frequency step limitations increase
Solution Approach 1:
The patent replaces mechanical divider circuits with an electronic phase comparison and calibration system. The calibration circuit uses phase detectors and digital signal processing to achieve frequency synchronization without physical dividers, thereby reducing device complexity and eliminating frequency step limitations inherent in divider-based approaches.
3Adaptability or versatility
If high frequency scaling is implemented between variable clock and fixed clock, then adaptability is improved, but clock alignment difficulty increases
Solution Approach 1:
The patent implements a feedback mechanism where the calibration circuit continuously monitors phase alignment between variable clock and fixed clock and dynamically adjusts phase corrections. The phase detector provides feedback signals that are processed to generate correction values, which are applied back to the PLL to maintain alignment despite high frequency scaling, making the alignment process automatic and reducing manual calibration difficulty.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables efficient clock synchronization across different frequencies, reducing complexity and allowing for dynamic frequency changes, thereby improving system operation and alignment in communication systems and processor-based systems.
Implementation Method 1
determining whether the variable clock and the reference clock are phase aligned based on the output of the comparison flip flop
Data Source
AI summary
A phase alignment system for aligning clocks is disclosed. The system includes a calibration circuit and a phase locked loop (PLL). The calibration circuit is configured to receive a variable clock and a reference clock; determine phase alignment based on metastability; determine phase misalignment and generate a phase shift upon determining phase misalignment. The PLL is configured to generate the variable clock and incorporate the phase shift.