Interface Circuit Timing Test Paths for Inaccessible 3D-IC Pins
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Solution Overview
Problem
Integrated circuit (IC) devices in directly attached configurations, such as 3D-ICs, pose challenges in testing input and output timing parameters due to inaccessible pins, making it difficult to ensure proper operation, especially when directly attached to another IC device.
Innovation Solution
Incorporating an internal test signal generator and test signal wires that allow for precise adjustment of clock and data signals, enabling the measurement of timing parameters like setup and hold times without impacting global clock signals, thereby isolating potential timing errors and allowing for separate testing of bonded IC dies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If IC devices are directly attached in a 3D-IC configuration, then device integration and compactness are improved, but accessibility of pins for testing deteriorates
Solution Approach 1:
The patent segments the IC device into functional blocks with dedicated test signal paths. Test signal wires are separated from global clock and data signal paths, allowing independent access to timing-critical signals for measurement without disrupting normal device operation or requiring physical pin access.
Solution Approach 2:
The patent introduces internal test signal generators and test signal wires as intermediaries between the inaccessible pins and the testing mechanism. These intermediaries provide indirect access to timing parameters by generating test signals internally and routing them through dedicated test paths that can be monitored without external pin access.
2Ease of operation
If global clock signals are used for testing, then timing parameter measurement is simplified, but interference with normal device operation increases
Solution Approach 1:
The patent extracts the testing function from the global clock signal system by introducing separate test signal generators. These dedicated test signal sources provide timing references solely for measurement purposes, eliminating any potential interference with the global clock signals that control normal device operation.
Solution Approach 2:
The patent segments the signaling system into distinct test signal paths and operational signal paths. Test signal wires carry timing reference signals separately from global clock and data signals, preventing interference between testing activities and normal device operation while allowing independent optimization of each path.
3Productivity
If timing parameters are not accurately tested, then manufacturing speed is maintained, but device reliability deteriorates
Solution Approach 1:
The patent implements preliminary timing verification through internal test signal generation and measurement capabilities built into the device structure. By performing timing parameter validation during or immediately after manufacturing through these integrated test paths, the need for extensive external testing is reduced, maintaining manufacturing speed while ensuring reliability.
Solution Approach 2:
The patent enables the IC device to perform self-testing of timing parameters through integrated test signal generators and measurement circuits. This self-service capability allows manufacturing to verify timing compliance without requiring complex external testing equipment or prolonged test cycles, thus maintaining productivity while ensuring device reliability.
Data Source
AI summary
A semiconductor IC device comprises a timing circuit to transfer a timing signal, the timing circuit being configured to receive a first test signal and to effect a delay in the timing signal in response to the first test signal, the first test signal including a first timing event. The semiconductor IC device further comprises an interface circuit configured to transfer the data signal in response to the timing signal, the interface circuit being further configured to receive a second test signal and to effect a delay in the data signal in response to the second test signal, the second test signal including a second timing event that is related to the first timing event according to a test criterion.