Scan Flip-Flop Clock-Gated Supply Sharing for Lower Dynamic Power
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Solution Overview
Problem
Current techniques for reducing dynamic power consumption in scan flip-flops (SFFs) within system-on-chip (SoC) structures either lead to performance degradation, increased static power consumption, or larger cell sizes, as they either reduce the positive voltage level or increase the load on the clock tree.
Innovation Solution
Incorporating shared clock-gated power supply transistors in scan flip-flop designs, which are controlled by clock signals to selectively connect voltage rails to both the driver and feedback paths of master and slave latches, reducing the load on the clock tree while maintaining performance and minimizing static power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the positive voltage level supplied to SFFs is reduced to decrease dynamic power consumption, then dynamic power consumption is reduced, but SFF performance degrades including slower switching speeds
Solution Approach 1:
The patent changes the voltage parameter by introducing a reduced voltage level (VDDX) that is lower than the normal operating voltage (VDD). This allows the SFF to operate at two different voltage levels: full voltage for high-performance mode and reduced voltage for low-power mode, thereby resolving the contradiction between power consumption and switching speed.
2Speed
If the threshold voltage of transistors is decreased to improve switching speed, then switching speed increases, but leakage current increases resulting in increased static power consumption
Solution Approach 1:
The patent employs dynamic voltage threshold adjustment by using different transistor threshold voltages in different operational modes. The SFF can switch between using low-threshold-voltage transistors (for high-speed operation) and high-threshold-voltage transistors (for low-leakage operation), thereby dynamically adapting to performance and power requirements.
3Use of energy by moving object
If techniques are used to reduce the load on the clock tree, then dynamic power consumption is reduced, but performance decreases, static power consumption increases, and SFF cell size increases
Solution Approach 1:
The patent segments the clock distribution by introducing separate clock inputs (CLK and CLKX) that can be independently controlled. This allows different portions of the SFF to be clocked differently, enabling fine-grained control over clock loading and power consumption without compromising overall performance.
Solution Approach 2:
The SFF is designed with multi-functionality to serve both high-performance and low-power modes. The same basic SFF structure can operate in different modes by selecting different voltage levels and clock configurations, eliminating the need for separate structures for different operational requirements.
4Reliability
If multiple clock pins are used to drive master and slave latches, then setup time is improved and isolation from poor input clock slews is achieved, but the load on the clock tree increases resulting in increased dynamic power consumption
Solution Approach 1:
The patent implements dynamic clock gating control where the clock signals to master and slave latches are selectively enabled or disabled based on operational mode. In low-power mode, clock gating is more aggressively applied to reduce switching activity and dynamic power consumption while maintaining reliable setup timing when clocks are active.
Data Source
AI summary
Disclosed are scan flip-flops (SFFs) that reduce the dynamic power consumption of a system-on-chip (SOC) that incorporates them. Each SFF includes a master latch and a slave latch, each having a driver, a feed-forward path and a feedback path. Each SFF further includes at least one shared clock-gated power supply transistor, which is controlled by either a clock signal or an inverted clock signal to selectively and simultaneously connect a voltage rail to both the driver from one latch and the feedback path of the other latch. The different SFF embodiments have different numbers of shared clock-gated power supply transistors and various other different features designed for optimal power and/or performance. For example, the different SFF embodiments have different types of slave latch drivers; different types of transistors; and/or different types of master latch drivers (e.g., a single-stage, multiple clock phase-dependent driver or a multi-stage, single clock phase-dependent driver).