Built-In Clock Jitter Circuit for Timing Margin Testing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional methods for determining processing system timing margins are inadequate as they fail to account for unique error sources in individual units and introduce additional timing errors through connectors, while laboratory tests are limited to specific conditions, neglecting environmental factors like temperature changes.
Innovation Solution
A built-in test circuit integrated into the processing system, comprising a second asynchronous clock signal generated by a programmable PLL device, which is processed with the main clock signal to determine system timing margin, using logic gates to output a third clock signal that mimics system clock with applied jitter, allowing for testing under various conditions without external connectors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional laboratory testing methods are used to determine timing margins, then timing margin measurement can be performed, but additional timing errors are introduced through connectors and external testing equipment
Solution Approach 1:
The test circuit is merged with the processing system by integrating the second clock circuit and logic circuit directly into the processing device. This eliminates the need for external connectors and testing equipment, thereby preventing additional timing errors from being introduced during measurement.
Solution Approach 2:
The processing system performs its own timing margin testing through the integrated built-in test circuit. The system uses its internal resources (clock circuits and logic circuits) to conduct self-testing, eliminating dependency on external testing equipment that would introduce additional errors.
2Reliability
If single production unit sampling is used for timing margin determination, then testing resources are conserved, but unique error sources and delays specific to each unit are not accounted for
Solution Approach 1:
Each production unit is equipped with its own built-in test circuit that can independently determine its timing margin characteristics. This allows each unit to be tested individually for its unique error sources and delays without requiring complex external testing setups.
3Adaptability or versatility
If laboratory testing is performed under fixed conditions, then testing setup is simplified, but environmental factors such as temperature changes that affect timing margin are not accounted for
Solution Approach 1:
The built-in test circuit enables dynamic testing under varying operational conditions including temperature changes. The circuit can perform timing margin measurements while the processing system operates under different environmental conditions, capturing the impact of temperature and other dynamic factors on timing margin.
4Measurement precision
If built-in test circuit is integrated into processing system, then timing error introduction is minimized, but circuit complexity increases
Solution Approach 1:
The test circuit components (second clock circuit and logic circuit) are merged with the existing processing system architecture. By sharing common resources and integrating closely with the main system, the additional complexity is minimized while maintaining measurement precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables accurate determination of system timing margins for individual processing units across a range of testing conditions, minimizing additional error introduction and accounting for environmental factors, thereby improving timing margin assessment.
Implementation Method 1
a programmable PLL receiving and modifying frequency of the oscillation signal and outputting the modified oscillation signal as the second clock signal
Data Source
AI summary
A built-in test circuit for testing a system timing margin of a processing device under-test is provided. The processing device includes a controller and first clock circuit, wherein the first clock circuit generates a first clock signal and the first clock signal is a main clock signal provided for operation of the processing device. The built-in test circuit includes a second clock circuit and a logic circuit, both of which are integrated with the processing device. The second clock circuit generates a second clock signal. The logic circuit processes the first and second clock signals and outputs a third clock signal. The third clock signal is used to determine system timing margin of the processing device.