Clock Frequency Modulation for ROC Digital-Analog Interference
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Solution Overview
Problem
Radio-on-chip (ROC) systems face interference issues due to digital circuits affecting radio frequency circuits, leading to worsened receiving sensitivity, ADC saturation, and EVM deterioration, as high-energy interfering pulses are generated near clock rising edges, potentially falling within radio frequency bands.
Innovation Solution
A clock frequency modulation method involving the determination of N digital clocks with specific frequency ratios, where the first digital clock is modulated into a periodic second digital clock using pseudo-random noise sequences to randomize frequency jitter, thereby spreading energy across a wide frequency range and reducing digital-analog interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single-phase clock is used in the digital circuit, then the clock signal is simple and easy to generate, but high-energy interfering pulses are generated near the rising edge, causing digital-analog interference
Solution Approach 1:
The single-phase clock is segmented into multiple phases (first digital clock and second digital clock with different phases). The digital circuit uses both clocks alternately, dividing the original single clock signal into multiple lower-energy clock signals that do not generate strong interfering pulses at the same time.
Solution Approach 2:
The patent implements periodic switching between the first and second digital clocks. Each clock operates periodically with a specific duty cycle, where the first clock is enabled during the first time period and the second clock is enabled during the second time period. This periodic action spreads the energy over time and prevents concentrated high-energy interference.
2Productivity
If clock frequency is increased to improve data processing speed, then productivity increases, but interfering pulse signals and their harmonics fall within radio frequency bands, worsening receiving sensitivity and EVM
Solution Approach 1:
The patent dynamically adjusts the clock frequency based on the operating mode. In normal mode, a higher clock frequency is used for fast data processing. In interference suppression mode, the clock frequency is reduced to push interfering harmonics out of the radio frequency bands. The system dynamically switches between these modes to balance productivity and interference suppression.
Solution Approach 2:
The patent changes the clock frequency parameter to control interference. By adjusting the frequency of the first and second digital clocks, the system can move the interfering pulse signals and their harmonics to different frequency locations. When interference is detected, the frequency is changed so that harmonics fall outside the sensitive radio frequency bands, thus protecting receiving sensitivity and EVM.
3Object-generated harmful factors
If multiple digital clocks with different phases are used to suppress interference, then digital-analog interference is reduced, but the clock system becomes more complex
Solution Approach 1:
The patent merges the generation of multiple phased clocks into a single unified system. A single clock generation unit produces both the first digital clock and the second digital clock with different phases, rather than using separate independent clock generators. This merging approach reduces the overall system complexity while still achieving interference suppression through phase diversity.
Solution Approach 2:
The clock generation unit is designed to be multi-functional, serving both as a simple single-phase clock generator and as a source of multiple phased clocks for interference suppression. The same hardware infrastructure supports both normal operation (single phase) and interference suppression mode (multiple phases), reducing the need for additional dedicated components and simplifying the overall system.
Data Source
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AI summary
Embodiments of the present invention provide a clock frequency modulation method and a clock frequency modulation apparatus. The method includes: determining N digital clocks according to a first digital clock of a system, where the N digital clocks includes a second digital clock and N-1 digital clocks except the second digital clock, and a sum of frequency ratios of the first digital clock to each of the N-1 digital clocks is equal to N-1 times a frequency ratio of the first digital clock to the second digital clock, where N is an integer greater than 2; and fitting, during a modulation period by using the N digital clocks, the first digital clock into the periodic second digital clock. The embodiments of the present invention use a clock frequency modulation technology to make energy concentrated in a frequency spread to a wider frequency range.