Clock Multiplexer with Reference Clock for Glitch-Free Switching
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Solution Overview
Problem
Conventional clock multiplexers require both input clock signals to be active for operation, leading to glitches and operational failures when one signal becomes inactive due to timing issues and synchronization mechanisms.
Innovation Solution
A clock multiplexer device with a clock switching timing controller that uses an independent reference clock signal to generate a switching trigger signal, allowing the device to select an active clock signal even if one of the input signals is inactive, thereby avoiding glitches through asynchronous clock switching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional clock multiplexer uses synchronization mechanisms to switch between clock signals, then clock switching can be controlled, but glitches occur when one clock signal becomes inactive
Solution Approach 1:
The patent introduces a third clock signal (clock2) as an intermediary backup when the primary clock signal (clock1) becomes inactive. The clock multiplexer switches from clock1 to clock2 through a controlled switching mechanism, avoiding direct confrontation between inactive clock signals and preventing glitches. This intermediary approach ensures continuous stable clocking without the harmful effects of undefined transition states.
2Device complexity
If clock multiplexer requires both clock signals to be active for operation, then switching control is simplified, but operational reliability decreases when one signal becomes inactive
Solution Approach 1:
The patent changes the operational parameters of the clock multiplexer by introducing a third clock signal (clock2) with different characteristics than clock1. When clock1 becomes inactive, the system transitions to using clock2, effectively changing the clock source parameter to maintain operation. This parameter change approach allows the system to adapt to different operational conditions without requiring complex control mechanisms, as the switching is driven by detection of clock signal activity states.
3Device complexity
If clock multiplexer uses conventional switching mechanism, then circuit structure is simple, but unpredictable transition states cause system instability
Solution Approach 1:
The patent implements preliminary action by detecting the inactive state of clock1 before the switching transition occurs. The detection circuit identifies when clock1 becomes inactive and triggers the switching mechanism to transition to clock2 in advance, avoiding undefined transition states. This preliminary detection and preparation ensures that the switching occurs at a well-defined moment, maintaining system stability without requiring complex circuit structures.
Data Source
AI summary
A clock multiplexer device, a controller and a storage device are provided. The clock multiplexer device comprises a clock switching timing controller and a clock multiplexer. The clock switching timing controller is configured to receive and operate at a reference clock signal being active and generate a clock switching trigger signal according to a plurality of clock signals, wherein the reference clock signal is independent of the plurality of clock signals. The clock multiplexer is for receiving the clock switching trigger signal and the plurality of clock signals, and selects one of the plurality of clock signals according to the clock switching trigger signal so as to output a target clock signal.