Synchronous Clock Multiplexer for Missing Clock Detection
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Solution Overview
Problem
Conventional synchronous clock multiplexers generate erroneous clock signals or fail to provide output when a selected clock signal is not available due to errors in clock sources, leading to improper operation of circuit modules and integrated circuits.
Innovation Solution
A synchronous clock multiplexer circuit that includes flip-flops, OR gates, AND gates, and logic circuits to detect the presence of clock input signals and generate an output clock signal based on availability, ensuring correct operation by selecting an alternative clock signal when the primary one is unavailable, and shutting down the unselected clock source to save power.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a synchronous clock multiplexer selects between clock signals based on a select signal transition, then it can provide clock signals from different sources to circuit modules, but it generates erroneous clock signals or fails to provide output when the selected clock signal is not available due to clock source errors
Solution Approach 1:
The patent applies preliminary action by detecting the availability of clock input signals before the select signal transition is completed. The detection circuit checks whether the selected clock signal is actually available at the input terminal before allowing the multiplexer to switch to that clock source, preventing erroneous output generation due to unavailable clock signals
Solution Approach 2:
The patent implements feedback by using the detected clock signal availability information to control the multiplexer switching operation. The detection circuit continuously monitors clock signal presence and feeds this information back to the control logic, which adjusts the switching behavior accordingly to maintain reliable output
2Reliability
If the synchronous clock multiplexer continuously monitors clock signal availability to prevent erroneous output, then it improves reliability, but it increases circuit complexity
Solution Approach 1:
The patent introduces an intermediary detection circuit that sits between the clock input terminals and the multiplexer core. This intermediary component specifically monitors clock signal availability and provides control signals to the multiplexer, achieving reliable operation without requiring complex modifications to the entire multiplexer structure
Data Source
AI summary
A synchronous clock multiplexer circuit detects the presence of an input clock signal whenever an input select signal changes state to select the input clock signal, and generates an output select signal, which is then used instead of the input select signal for selecting an input clock signal as an output clock signal. The output select signal stays in a logic high state to select a second input clock signal when the input select signal transitions from high to low to select a first input clock signal but the first input clock signal is not present. The output select signal stays in a logic low state to select the first input clock signal when the input select signal transitions from low to high to select the second input clock signal but the second input clock signal is not present.