Clock Path Delay Compensation for Power Supply Phase Drift
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Solution Overview
Problem
Memory devices face timing variations in clock signals due to power supply sensitivities, which can cause operational issues as different components in the clock path respond differently to voltage and current variations, leading to phase drift and synchronization problems.
Innovation Solution
A delay compensation circuit is implemented that adjusts the delay of clock signals based on phase differences detected between forward and feedback clock paths, using switch circuits and timing circuits with predictable delay power supply sensitivities to compensate for variations in power supply, ensuring the clock signals remain in phase.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If delay circuits are added to adjust clock timing, then clock signal timing can be adjusted, but timing variation increases due to power supply sensitivity
Solution Approach 1:
The patent implements a feedback mechanism where the output of the delay circuit is fed back to a second input of the XOR gate. This feedback loop allows the circuit to automatically adjust and compensate for timing variations caused by power supply sensitivity, resolving the contradiction between timing adjustability and timing stability.
Solution Approach 2:
The patent changes the operating parameters of the delay circuit by applying complementary signals to its inputs. By controlling the delay circuit with signals that are inversely related to the clock signal, the circuit can adjust its delay characteristic dynamically to compensate for power supply variations, achieving both timing adjustment and stability.
2Measurement precision
If multiple delay circuits are used to achieve precise timing control, then timing precision is improved, but power supply sensitivity effects accumulate
Solution Approach 1:
The patent merges the function of multiple delay circuits into a single delay circuit by using the feedback mechanism. Instead of cascading multiple delay circuits which would accumulate power supply sensitivity effects, the feedback approach allows one delay circuit to perform the cumulative timing adjustment function while compensating for its own power supply sensitivity through the feedback loop.
Solution Approach 2:
The patent converts the harmful effect of power supply sensitivity into a beneficial feature by using the same sensitivity characteristic in the feedback path. The delay circuit's power supply sensitivity, which would normally cause timing errors, is instead used to automatically compensate for timing variations through the feedback mechanism, turning the harmful factor into a self-correcting feature.
3Adaptability or versatility
If delay circuits with different power supply sensitivities are used, then timing flexibility is improved, but synchronization accuracy deteriorates
Solution Approach 1:
The patent applies local quality by using the same delay circuit for both the forward path (affecting timing flexibility) and the feedback path (affecting synchronization accuracy). This ensures that the power supply sensitivity characteristics are consistent between the two paths, allowing timing flexibility to be achieved without sacrificing synchronization accuracy.
Solution Approach 2:
The patent ensures homogeneity by using identical delay circuitry in both the main clock path and the feedback path. This homogeneous design ensures that both paths respond similarly to power supply variations, maintaining synchronization accuracy while still providing timing flexibility through the adjustable delay element.
Data Source
AI summary
Apparatuses and methods for compensating for differing power supply sensitivities of a circuit in a clock path. One such method includes altering signal timing of at least one of reference and feedback clock signals differently according to variations in power supply voltage to compensate for differences in delay power supply sensitivities of delays of a forward clock path and of a feedback clock path. Another example method includes providing an output clock signal in phase with an input clock signal and compensating for delay error between delays used in providing at least some of the delay of the output clock signal relative to the input clock signal by providing delays having power supply sensitivities resulting in a combined power supply sensitivity that is inverse to the delay error.