Clock Phase Detection via Binary Sampling and Interval Convergence
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Solution Overview
Problem
Existing phase detection methods in wireless communication systems, particularly in 5G MIMO technology, suffer from low precision and complexity, especially with high-frequency clock signals, and existing solutions like PFDs and NCOs fail to provide adequate phase information efficiently.
Innovation Solution
A phase detection method involving binary sequence sampling, phase interval determination, and standardization operations to achieve high precision without complex computations, using a phase detection apparatus with modules for sampling, interval determination, and convergence.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional phase detection methods (PFD, NCO) are used, then phase detection can be performed, but phase detection precision is low and computational complexity is high
Solution Approach 1:
The phase detection process is segmented into distinct stages: sampling the clock signal to generate binary sequences, determining phase intervals from these sequences, and standardizing phase information through convergence operations. This segmentation transforms a complex continuous phase detection problem into discrete, manageable digital processing steps, achieving high precision without excessive computational complexity
Solution Approach 2:
The patent replaces traditional analog or complex digital phase detection mechanisms (PFD, NCO) with a simplified digital sampling and interval determination system. By substituting the mechanical/computational complexity of traditional methods with straightforward binary sequence analysis and phase interval standardization, the system achieves both high precision and low computational overhead
2Measurement precision
If phase detection precision is improved, then multi-channel synchronization effect is enhanced, but algorithm complexity and circuit implementation difficulty increase
Solution Approach 1:
The patent changes the fundamental parameters of phase detection from continuous analog signal analysis to discrete binary sequence sampling and phase interval determination. By operating in the digital domain with standardized phase intervals, the system achieves high precision while maintaining simple circuit implementation through standard digital logic operations
Solution Approach 2:
The patent uses binary sequences as digital copies of the clock signal phases, replacing the need for complex analog signal processing. These binary sequences capture the essential phase information in a simplified digital form that can be easily processed and standardized, achieving high precision with straightforward circuitry
3Speed
If conventional phase detection schemes are used, then basic phase information can be obtained, but fast phase convergence cannot be achieved
Solution Approach 1:
The patent employs periodic sampling of the clock signal to generate binary sequences at regular intervals. This periodic action, combined with phase interval standardization and convergence operations, enables both fast phase convergence and high detection precision by systematically processing phase information over multiple sampling periods
Solution Approach 2:
The phase interval standardization and convergence process incorporates feedback mechanisms where phase information from previous sampling periods informs subsequent phase determinations. This feedback loop accelerates phase convergence while maintaining high precision through iterative refinement of phase estimates
Data Source
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AI summary
A phase detection method and apparatus, and a storage medium and an electronic apparatus are provided. The method includes that: a sampling operation is performed on a clock signal to be detected to obtain binary sequences (S12); phase intervals of the clock signal to be detected in initial sampling periods are determined, according to the binary sequences, as first phase intervals (S14); based on a reference phase interval in the first phase intervals, a standardization operation is performed on other phase intervals in the first phase intervals to obtain second phase intervals, wherein the reference phase interval is a phase interval determined within a first sampling period after the sampling operation is triggered, and the other phase intervals are phase intervals determined within sampling periods following the first sampling period after the sampling operation is triggered (S16); and the second phase intervals are converged, and phase information of the clock signal to be detected is obtained according to the converged second phase intervals (S18).