Clock Phase Error Circuit for Reliable Clock Domain Crossing
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Solution Overview
Problem
In integrated circuit design, marginal PLL circuit design and environmental variations can lead to improper clock domain crossing, causing operational failures due to unquantified peak phase errors between disparate clock signals.
Innovation Solution
A phase error circuit with phase difference logic and delay/register logic is used to measure peak phase error by comparing clock signals, providing a pulse difference signal and registering delay bits to determine the phase error value, enabling adjustments to ensure proper operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If PLL circuits are used to multiply reference clock frequency to generate disparate clock signals, then clock domain crossing capability is improved, but phase error between clock signals increases causing timing failures
Solution Approach 1:
The patent applies preliminary action by measuring the phase error between clock signals before actual data transfer operations. The phase error measurement circuit continuously monitors and quantifies phase differences between clock domains, allowing the system to know in advance whether timing conditions are acceptable for safe data transfer, thus preventing timing failures before they occur.
Solution Approach 2:
The patent implements feedback by using the measured phase error information to control whether data transfer between clock domains should proceed. The phase error measurement results feed back to the clock domain crossing logic, enabling dynamic adjustment of transfer operations based on real-time timing conditions, ensuring reliable operation despite phase variations.
2Reliability
If phase error measurement is implemented to ensure timing accuracy, then reliability is improved, but device complexity increases due to additional measurement circuits
Solution Approach 1:
The patent applies universality by designing a phase error measurement circuit that can measure phase differences between any pair of clock signals from different clock domains. This single multi-functional circuit structure can be used to measure phase errors across multiple clock domain interfaces, reducing the need for separate measurement circuits for each interface and thereby limiting the increase in overall device complexity.
Data Source
AI summary
A phase error circuit including phase difference logic and delay and register logic. The phase difference logic provides a pulse difference signal including at least one difference pulse indicative of a timing difference between selected edges of a pair of clock signals. The delay and register logic receives the pulse difference signal and provides a phase error value representing phase error between the clock signals. The delay and register logic may include a delay line with multiple delay cells and taps coupled in series in which each tap provides an output state of a delay cell. The register logic registers a state of each tap to provide delay bits in response to each trailing edge of the difference pulses. Each delay bit may remain set until reset so that the longest pulse difference signal is registered to provide the peak phase error.