Serial Clock-Phase Encoding for Multiplexed I2S Streams
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Solution Overview
Problem
Conventional methods face challenges in efficiently transmitting multiple clock and data streams over a serial bus interface while meeting latency and jitter requirements, particularly in systems like USB, due to the need for complex receivers and alignment of independent reference clocks.
Innovation Solution
A low latency, low bandwidth serial channel encoding and decoding method that encodes clock phase information with data stream signals, allowing reconstruction at the receiver without bit modification, using a frame-based architecture to aggregate and de-aggregate streams over a single serial communication link.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If parallel wired channel is used to transmit multiple clock and data streams, then transmission simplicity is improved, but device complexity increases due to requirements for multiple channels and complex receivers
Solution Approach 1:
The patent merges multiple independent clock and data streams into a single multiplexed serial channel. The host device combines multiple I2S streams (audio, data, control) that were previously transmitted over separate parallel channels into one aggregated serial stream, reducing the number of physical channels while maintaining all functionality.
Solution Approach 2:
The serial communication channel is designed to handle multiple types of streams universally - audio data, control signals, and other data streams all share the same transmission medium. The receiver is configured to de-multiplex and process different stream types from this single channel, making the system more versatile.
2Adaptability or versatility
If independent reference clocks are used for each stream, then stream independence is improved, but synchronization difficulty increases due to clock alignment requirements
Solution Approach 1:
The patent introduces a master reference clock as an intermediary that all slave streams synchronize to. Instead of trying to align multiple independent clocks directly, each stream uses the master clock as a common reference point, simplifying the synchronization process while maintaining stream independence.
Solution Approach 2:
The synchronization system is segmented into a master clock domain and multiple slave clock domains. Each stream is assigned to a specific clock domain hierarchy level, allowing independent operation within domains while maintaining coordination across domains through the master clock reference.
3Productivity
If multiple streams are transmitted over a single serial channel, then bandwidth efficiency is improved, but transmission complexity increases due to multiplexing and de-multiplexing requirements
Solution Approach 1:
The multiplexing scheme uses periodic time-division multiplexing where different streams are assigned specific time slots within a repeating frame structure. Each stream is transmitted during its allocated time period, and the pattern repeats continuously, making the multiplexing process systematic and manageable.
Solution Approach 2:
The host device performs preliminary multiplexing of all streams before transmission, organizing data into predefined frame structures with allocated time slots for each stream type. This pre-organization simplifies the transmission process and makes de-multiplexing at the receiver more straightforward.
4Productivity
If clock phase information is encoded with data stream, then transmission efficiency is improved, but encoding complexity increases due to phase detection and encoding requirements
Solution Approach 1:
The patent merges clock phase information with data stream transmission by encoding phase details within the data frames themselves. Instead of transmitting clock and data separately, the phase information is embedded in the data portion of each frame, consolidating multiple information types into a single streamlined transmission.
Solution Approach 2:
The encoding scheme changes the representation of clock phase from a separate signal parameter to an encoded parameter within the data stream. Phase information is converted into discrete values that can be represented using standard data encoding formats, making it compatible with serial transmission protocols.
Data Source
AI summary
A method, apparatus, and system are disclosed for a host to process and transmit one or more streams having a data signal and bit clock signal over a serial channel to a receiver by detecting a count and timing location for one or more clock edge transitions in the bit clock signal with respect to a pre-negotiated duration spanning over one or multiple aggregated frames which are transmitted over the serial channel, and then coding the count and timing location with one or more corresponding data values from the data signal into a multi-bit clock phase data codeword which is inserted into one of the aggregated frame that is transmitted over the serial channel to the receiver.