Clock Phase Initialization for Clock Data Recovery Circuits
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Solution Overview
Problem
Conventional clock and data recovery (CDR) circuits face challenges in accurately initializing the phase of the recovered clock signal, which is crucial for sampling the analog signal near the middle of unit intervals to avoid ambiguities, especially when the initial phase is not set sufficiently near the center, leading to suboptimal performance.
Innovation Solution
The proposed solution involves an initialization mode in the CDR circuitry where the phase of the clock signal is systematically adjusted across multiple phases to determine the optimal initial phase for transitioning to the on-line mode, ensuring accurate timing for data recovery. This is achieved by generating and selecting the clock phase corresponding to the largest sum of absolute ADC samples, which can be done through various techniques including sequential phase shifting, parallel sampling, or using digital interpolation filters.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional CDR circuits use phase-adjustment circuitry to control the phase of the recovered clock signal, then the phase can be accurately controlled after initial setting, but the circuit fails to function properly when the initial phase is not set sufficiently near the middle of the unit intervals
Solution Approach 1:
The patent applies preliminary action by implementing an initialization mode that proactively sets the clock phase to the optimal center position before the CDR circuit begins normal operation. This preliminary phase alignment ensures that when the phase-adjustment circuitry starts working, the clock phase is already correctly positioned, eliminating the requirement for manual initial phase setup and ensuring reliable operation from startup.
2Measurement precision
If the initial phase is set near the middle of unit intervals, then accurate data sampling can be achieved, but the system becomes sensitive to phase drift and requires precise initial configuration
Solution Approach 1:
The patent applies self-service by designing an initialization mode that automatically determines and sets the optimal clock phase without external intervention. The system uses the received analog signal itself to identify the center of unit intervals and automatically aligns the clock phase accordingly, making the circuit self-configuring and eliminating complex manual phase initialization procedures while maintaining high sampling timing accuracy.
Data Source
AI summary
In order to initialize the phase of the recovered clock signal used in clock-and-data recovery (CDR) circuitry, the normal, on-line CDR processing is disabled. The sum of the absolute values of analog-to-digital converter (ADC) samples are generated for different clock phases over each unit interval (UI) of the analog signal sampled by the ADC for a specified period of time. The phase corresponding to the maximum sum is selected as the initial phase for the recovered clock signal for enabled, on-line CDR processing, which among other things, automatically updates the clock phase to ensure that the ADC samples the analog signal near the center of each UI.