Clock Phase Adjustment Circuit Using an Intermediate Reference
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Solution Overview
Problem
Conventional phase adjustment circuits face instability in phase determination when enhancing phase resolution, leading to repeated phase inversion operations due to clock jitter, especially when generating a 50% duty-cycle phase-adjusted clock with high frequency and high phase resolution.
Innovation Solution
A phase adjustment circuit generates an intermediate reference clock apart from both the phase reference clock and the phase-adjusted clock, controlling the intermediate reference clock to be in a desired phase relationship with the phase reference clock, and subsequently controlling the phase-adjusted clock to match the intermediate reference clock, thereby stabilizing phase determination without direct phase comparison between the reference and adjusted clocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If phase comparison is performed directly between the phase reference clock and the phase-adjusted clock to determine phase relationship, then phase control can be achieved, but clock jitter causes repeated phase inversion operations when phase resolution is enhanced
Solution Approach 1:
The patent introduces an intermediate reference clock as a mediator between the phase reference clock and the phase-adjusted clock. The phase relationship determination is performed between the intermediate reference clock and the phase-adjusted clock, rather than directly between the phase reference clock and phase-adjusted clock. This intermediary approach isolates the phase determination process from clock jitter affecting the phase reference clock, thereby stabilizing phase control while maintaining high phase resolution.
2Manufacturing precision
If a 1/2 frequency division circuit is used to generate a 50% duty-cycle clock, then the duty cycle is corrected to 50%, but the output phase becomes uncertain with respect to the phase reference clock
Solution Approach 1:
The patent generates an intermediate reference clock in advance with a predetermined phase relationship to the phase reference clock before the phase adjustment operation. This preliminary establishment of a stable phase reference (the intermediate reference clock) allows the subsequent phase adjustment circuit to operate with deterministic phase relationships, eliminating the uncertainty that would otherwise result from the 1/2 frequency division circuit's initial state dependency.
Data Source
AI summary
In a phase adjustment circuit that divides the frequency of a double-frequency clock to obtain a 50% duty-cycle clock, a first ½ frequency division circuit having a phase inversion function generates an intermediate reference clock apart in phase from both a phase reference clock and a phase-adjusted clock. A first phase control circuit controls the phase of the intermediate reference clock to be in a desired phase state with respect to the phase reference clock. A second phase control circuit controls the phase of the phase-adjusted clock to be in a desired phase state with respect to the intermediate reference clock. Thus, when the phase-adjusted clock is adjusted to be close in phase to the phase reference clock, the phase difference between these clocks can be determined correctly and stably even if it varies due to clock jitter.