Multi-Phase Clock Alignment Using Reference Time Events

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Solution Overview

Problem

Existing multi-phase clock systems are limited by the accuracy of time interval measurement, which becomes less accurate at higher frequencies, restricting their operational clock frequency and suitability for high-speed applications.

Innovation Solution

A multi-phase clock system that uses a reference clock signal with a different frequency to determine desired time events, allowing for accurate de-skewing of clock signals through a comparator and de-skew circuit, eliminating the need for direct measurement of short time intervals and enabling operation at higher frequencies.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If time interval measurement is used to measure skew between clock phases, then skew measurement capability is provided, but measurement precision deteriorates at higher frequencies

Engineering Contradiction:
Improveoperational clock frequencyVSAvoidskew measurement accuracy
Core Design Contradiction:
SpeedVSMeasurement precision

Solution Approach 1:

The patent introduces a reference clock signal as an intermediary element to indirectly measure skew. Instead of directly measuring the time interval between high-frequency clock phases (which becomes inaccurate at high frequencies), the system uses a lower frequency reference clock to generate reference time events that correspond to desired clock edge positions. The comparator then measures the time difference between these reference time events and actual clock edges, providing accurate skew measurement without being limited by the high frequency of the original clock signals.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Measurement precision

If direct measurement of short time intervals is performed, then skew calibration is achieved, but measurement accuracy decreases at higher frequencies

Engineering Contradiction:
Improvephase measurement accuracyVSAvoidclock frequency
Core Design Contradiction:
Measurement precisionVSSpeed

Solution Approach 1:

The patent transforms the measurement problem from the time domain to a frequency domain relationship. By establishing a fixed frequency relationship between the reference clock and the multi-phase clock (where the reference clock frequency is a fraction of the multi-phase clock frequency), the system converts the difficult task of measuring short time intervals at high frequency into the easier task of measuring time intervals at lower frequency, while maintaining accuracy through the known frequency ratio.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Productivity

If high frequency operation is implemented, then speed of operation is improved, but time measurement accuracy deteriorates

Engineering Contradiction:
Improvespeed of operationVSAvoidtime event measurement accuracy
Core Design Contradiction:
ProductivityVSMeasurement precision

Solution Approach 1:

The system performs preliminary action by pre-establishing the frequency relationship between the reference clock and the multi-phase clock before actual skew measurement begins. The reference clock is configured with a frequency that is a specific fraction of the multi-phase clock frequency, which pre-determines the expected timing relationships. This preliminary configuration allows the comparator to accurately measure skew by comparing actual clock edges against pre-calculated reference time events, enabling high-speed operation without sacrificing measurement precision.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentEP2145243B1Multi-phase clock system
Publication Date: 2010.07.21 NXP BV
  • EP2145243B1 patent drawingFigure 1a~1b
  • EP2145243B1 patent drawingFigure 2a~2b
  • EP2145243B1 patent drawingFigure 3

AI summary

The invention relates to multi-phase clock system for receiving a plurality of clock signals (CLKo-n) comprising actual time events (aTE) defining different clock phases, the clock signals all having a same clock frequency but different clock phases, the system further arranged for receiving a reference clock signal (REFCLK) for providing reference time events (rTE) for the plurality of clock signals (CLKo-n), the reference clock signal (REFCLK) having a reference frequency different from the clock frequency, the reference frequency being selected such that each one of the subsequent reference time events (rTE) coincides with a desired time event (dTE) for a single one of the plurality of clock signals (CLKo-n).