Programmable Clock Phase Circuit Using a Digitally Calibrated Ring Oscillator
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Solution Overview
Problem
Existing clock phase generation circuits for SAR ADCs rely on complex analog circuits, such as DLLs, which do not scale well with reduced process nodes, limiting their performance and scalability.
Innovation Solution
A digitally calibrated programmable clock phase generation circuit using a gated ring oscillator that provides a reference clock with a higher fundamental frequency than the input clock, allowing for programmable adjustment of clock edges and duty cycles without a DLL, enabling scalable and rapid edge clock generation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a DLL (delay-locked loop) is used to generate multiple clock edges within a clock period, then the clock phase generation capability is improved, but the device complexity and scalability to smaller process nodes deteriorate
Solution Approach 1:
The patent replaces the analog DLL circuit with a digital clock phase generation circuit that uses a ring oscillator and digital logic elements (D-latches, multiplexers) to generate multiple clock edges. This substitution of analog with digital circuitry resolves the contradiction by maintaining clock phase generation capability while reducing complexity and improving scalability to smaller process nodes.
Solution Approach 2:
The patent employs a programmable ring oscillator whose oscillation frequency can be adjusted by changing the number of inversion stages (N). By programmatically controlling the oscillator frequency and using digital counters to divide this frequency, the circuit can generate multiple clock edges with different phases. This parameter-based control approach provides versatility without requiring complex analog circuitry.
2Manufacturing precision
If the process node is reduced to smaller critical dimensions, then the manufacturing precision and integration density are improved, but the performance of analog circuits in DLLs deteriorates
Solution Approach 1:
The patent replaces analog DLL circuits with a digital implementation using a ring oscillator and digital logic. This substitution eliminates the reliability issues of analog circuits at smaller process nodes while maintaining the ability to generate multiple clock edges. The digital circuitry is inherently more robust to process variations and scales better to smaller dimensions.
Solution Approach 2:
The patent uses a ring oscillator that can be replicated and programmed to generate different clock phases. By copying the basic oscillator and counter logic structure and programmatically configuring it, the system achieves reliable operation at smaller process nodes without requiring precise analog circuit design.
3Adaptability or versatility
If a gated ring oscillator with higher fundamental frequency is used, then the programmability and edge clock generation flexibility are improved, but the use of energy increases
Solution Approach 1:
The patent uses a gated ring oscillator that operates periodically, being enabled only when calibration or clock edge generation is needed. The oscillator generates a high-frequency reference clock that is then divided down using counters to produce the desired clock edges. This periodic operation rather than continuous operation reduces power consumption while maintaining programmability.
Solution Approach 2:
The patent implements a dynamically controllable ring oscillator where the number of inversion stages (N) can be programmatically adjusted to change the oscillation frequency. This dynamic configurability allows the circuit to adapt to different power and performance requirements, consuming more power only when higher frequency and flexibility are needed.
Data Source
AI summary
An integrated circuit that includes a generating circuit is described. During operation, the generating circuit may provide an edge clock having a target phase within a clock period of an input clock, where the generating circuit does not include a delay-locked loop (DLL). For example, the generating circuit may include a gated ring oscillator that provides a reference clock having a first fundamental frequency that is larger than a second fundamental frequency of the input clock. Note that the gated ring oscillator may be programmable to adjust the first fundamental frequency within a predefined range of values. Moreover, the generating circuit may include a control circuit that determines a reference count of a number of edges of the reference clock within a reference period of the reference clock.