Clock Phase Encoding for Low-Jitter Stream Multiplexing

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Solution Overview

Problem

Conventional methods face challenges in efficiently transmitting multiple clock and data streams over a serial bus interface while meeting latency and jitter requirements, particularly when aggregating and demultiplexing isochronous or bursty streams without the need for elastic buffers or bit-level re-timers.

Innovation Solution

Encoding clock phase information with data stream signals to reconstruct clock and data streams at the receiver, using a low latency, low bandwidth serial channel encoding and decoding method that aggregates streams over a multiplexed link without decoding or storing the incoming stream.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If multiple clock and data streams are transmitted over a parallel wired channel, then transmission simplicity is improved, but bandwidth efficiency deteriorates when using a serial bus interface

Engineering Contradiction:
Improvetransmission simplicityVSAvoidbandwidth efficiency
Core Design Contradiction:
Ease of operationVSQuantity of substance

Solution Approach 1:

The patent combines multiple clock and data streams into a single multiplexed serial stream. The encoder aggregates multiple input streams (including isochronous, bursty, and available bit rate streams) onto one serial communication link, thereby improving bandwidth efficiency while maintaining transmission simplicity through unified serial interface operation.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The serial bus interface is designed to handle multiple types of streams (isochronous, bursty, available bit rate) simultaneously through a single unified protocol. This multi-functional capability allows the same serial interface to efficiently transmit different data types without requiring separate dedicated channels for each stream type.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Quantity of substance

If streams are aggregated and demultiplexed over a serial bus interface, then bandwidth efficiency is improved, but latency and jitter requirements become harder to meet

Engineering Contradiction:
Improvebandwidth efficiencyVSAvoidlatency and jitter
Core Design Contradiction:
Quantity of substanceVSLoss of time

Solution Approach 1:

The encoder performs preliminary encoding of clock phase information into the data stream before transmission. By pre-encoding the timing information, the receiver can accurately reconstruct the original clock signals without requiring complex real-time timing recovery mechanisms, thereby reducing jitter and meeting latency requirements while maintaining bandwidth efficiency.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent introduces clock phase encoding as an intermediary mechanism that carries timing information within the data stream itself. This intermediary encoding allows the receiver to extract precise timing information without requiring separate clock channels or complex synchronization protocols, thus maintaining low latency and jitter while achieving efficient serial multiplexing.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Measurement precision

If clock phase information is encoded with data stream signals, then reconstruction accuracy is improved, but encoding complexity increases

Engineering Contradiction:
Improvereconstruction accuracyVSAvoidencoding complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The encoding process is segmented into distinct functional blocks: clock edge detection, timing interval measurement, phase difference calculation, and encoded value generation. This segmentation allows each function to be implemented independently with well-defined interfaces, reducing overall encoding complexity while maintaining high reconstruction accuracy through specialized processing at each stage.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentEP4679278A1Method and apparatus to send and reconstruct an isochronous or bursty stream across a multiplexed link
Publication Date: 2026.01.14 NXP USA INC
  • EP4679278A1 patent drawingFigure 1
  • EP4679278A1 patent drawingFigure 2
  • EP4679278A1 patent drawingFigure 3

AI summary

A method, apparatus, and system are disclosed for a host to process and transmit one or more streams having a data signal and bit clock signal over a serial channel to a receiver by detecting a count and timing location for one or more clock edge transitions in the bit clock signal with respect to a pre-negotiated duration spanning over one or multiple aggregated frames which are transmitted over the serial channel, and then coding the count and timing location with one or more corresponding data values from the data signal into a multi-bit clock phase data codeword which is inserted into one of the aggregated frame that is transmitted over the serial channel to the receiver.