Digital Clock Recovery Circuit for Fast Frequency Deviation Locking
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Solution Overview
Problem
Existing phase error-based CDR circuits struggle to quickly and accurately capture frequency deviations in scenarios with large frequency deviations, particularly in spread spectrum clocking, leading to prolonged capture times or incorrect locking.
Innovation Solution
A circuit and method incorporating an analog-to-digital converter, error detector, frequency deviation detector, loop filter, and phase interpolator, which utilize phase error estimation values to calculate frequency deviation estimation, enabling rapid and accurate clock synchronization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If phase error-based CDR circuits are used for clock data recovery, then the circuit can effectively capture frequency deviation within a limited range, but the convergence frequency range decreases and capture time increases as communication rates increase due to loop delay
Solution Approach 1:
The patent segments the frequency deviation capture process into two distinct stages: a fast capture stage using a frequency deviation detector to quickly acquire large frequency deviations, and a fine tuning stage using the traditional phase error detector to precisely track small deviations. This segmentation allows the system to handle both large initial deviations and small tracking errors efficiently, resolving the contradiction between capture speed and accuracy.
Solution Approach 2:
The patent implements preliminary action by using the frequency deviation detector to perform initial frequency acquisition before the phase error detector takes over for fine tracking. The frequency deviation detector pre-processes the signal to estimate and compensate for large frequency deviations, allowing the phase error detector to start from a near-locked state rather than from a large deviation, thereby significantly reducing capture time.
2Reliability
If phase error-based CDR circuits are used, then the circuit can lock onto the clock frequency, but it may require multiple initializations with different frequency deviations or lock onto an incorrect bias frequency in scenarios with large frequency deviations
Solution Approach 1:
The patent introduces the frequency deviation detector as an intermediary component between the input signal and the phase error detector. This intermediary performs preliminary frequency deviation estimation and compensation, ensuring that the phase error detector receives a pre-conditioned signal with reduced frequency deviation. This eliminates the need for multiple initializations and prevents incorrect locking, thereby improving reliability without significantly increasing system complexity.
3Adaptability or versatility
If the sampling clock frequency is adjusted to capture frequency deviation, then the locking range can be extended, but the loop delay increases and convergence range decreases
Solution Approach 1:
The patent segments the frequency adjustment function between two detectors: the frequency deviation detector handles large frequency adjustments to extend the locking range, while the phase error detector handles small frequency adjustments for fine tracking. This segmentation allows the system to achieve a wide locking range without the loop delay penalties that would result from using a single detector for all frequency adjustments.
Data Source
AI summary
A circuit and a method for digital clock data recovery are provided. The circuit comprises an analog-to-digital converter, an error detector, a frequency deviation detector, a loop filter, a phase code generator, and a phase interpolator. The analog-to-digital converter samples an analog input signal under the control of a sampling clock signal to obtain a sampled signal, and converts the sampled signal into a digital signal. The error detector performs phase error detection based on the digital signal to obtain phase error estimation values. The frequency deviation detector obtains a frequency deviation estimation value based on the phase error estimation values. The loop filter filters and outputs a filtered signal based on the phase error estimation values and the frequency deviation estimation value. The phase code generator generates a phase code based on the filtered signal. The phase interpolator generates the sampling clock signal based on the phase code.