Multi-Phase Clock Recovery for Fast Locking Under High Jitter
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Solution Overview
Problem
Existing clock and data recovery circuits (CDRs) face issues with high jitter tolerance and slow phase locking, leading to data recovery errors and inefficient initial locking in high-speed serial communication systems.
Innovation Solution
A clock and data recovery circuit that samples clock phase signals on data input signal edges, evaluates the timing relationship, and produces a clock output signal using phase adjust and select modules to achieve fast phase locking and high jitter tolerance, with optional glitch suppression mechanisms.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If prior CDR designs are used, then the circuit can operate with standard jitter tolerance, but the circuit produces data recovery errors under large instantaneous timing jitter conditions
Solution Approach 1:
The patent divides the clock signal into multiple phase segments (first clock phase, second clock phase, third clock phase, fourth clock phase) separated by phase differences. This segmentation allows the circuit to sample data at multiple different timing points within a clock cycle, enabling it to find the optimal sampling point even when large timing jitter is present, thereby maintaining data recovery accuracy under jitter conditions.
Solution Approach 2:
The patent implements dynamic phase selection where the CDR circuit continuously evaluates timing relationships between data transitions and clock phases, then dynamically selects the optimal clock phase for data sampling. This dynamic adaptation allows the circuit to track and compensate for timing jitter in real-time, improving reliability under varying jitter conditions.
2Speed
If prior CDR designs are used, then the circuit can recover clock signals, but the initial locking to input data is slow
Solution Approach 1:
The patent generates multiple clock phase signals in advance (first, second, third, and fourth clock phases with predetermined phase differences) before data recovery begins. This preliminary preparation of multiple phase options enables the circuit to quickly evaluate timing relationships and lock onto the optimal phase immediately upon receiving input data, significantly reducing initial locking time.
Solution Approach 2:
The patent uses periodic sampling of data at multiple clock phases to evaluate timing relationships. By periodically checking timing alignment at different phases and selecting the best match, the circuit achieves fast initial locking without requiring complex iterative adjustments, reducing the time lost during the locking process.
3Object-affected harmful factors
If complex circuitry is added to handle timing jitter, then jitter tolerance improves, but the device complexity increases
Solution Approach 1:
The patent combines multiple clock phase generation, data sampling, timing evaluation, and clock selection functions into a unified CDR circuit architecture. By merging these functions that work together to handle timing jitter, the circuit achieves high jitter tolerance without proportionally increasing complexity, as the components are integrated and coordinated through a systematic approach.
Solution Approach 2:
The patent designs a multi-functional CDR circuit that simultaneously performs clock recovery, phase evaluation, timing jitter compensation, and data sampling using a unified architecture. The same circuit structure handles multiple functions related to jitter tolerance, avoiding the need for separate dedicated circuits for each function and thereby limiting overall device complexity.
Data Source
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AI summary
Systems and methods for recovering clock and data from a data input signal are disclosed that sample a plurality of clock phase signals with the data input signal to determine a timing relationship between the data input signal and the clock phase signals and use the determined to timing relationship to select one of the clock phase signals to use for sampling the data input signal to produce recovered data. The CDR can include a glitch suppression module to suppress glitches on the clock output signal that could be caused by large instantaneous jitter on the data input signal. A clock and data recovery circuit (CDR) using these methods can quickly lock to a new data input signal and can reliably receive data when there is large instantaneous timing jitter on the data input signal.