Clock Recovery Circuit with Multi-Phase Switching for Faster Tracking

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Solution Overview

Problem

Feedback-based data recovery circuits in digital televisions face challenges in achieving timely optimal sampling phase and prolonged tracking times due to independent voltage controlled oscillation and data recovery loops.

Innovation Solution

A data recovery circuit incorporating a voltage control oscillator, multiplexer, phase-frequency detector, charge pump, loop filter, phase detector, and digital low-pass filter, where the digital low-pass filter generates a selection signal to adjust the multiplexer phase and clear accumulated phase errors, enhancing tracking speed and reducing tracking time.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If independent voltage controlled oscillation loop and data recovery loop are used, then bandwidth design flexibility is improved, but tracking time is prolonged

Engineering Contradiction:
Improvebandwidth design flexibilityVSAvoidtracking time
Core Design Contradiction:
Adaptability or versatilityVSLoss of time

Solution Approach 1:

The patent merges the voltage controlled oscillation loop and data recovery loop into a unified structure where the VCO is shared between both loops. This allows the system to maintain independent bandwidth design flexibility while reducing tracking time through coordinated operation of the loops, eliminating the delays associated with completely independent loop operations.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent implements a feedback mechanism where the data recovery loop provides phase error information back to the VCO, enabling the system to dynamically adjust and converge to the optimal sampling phase more quickly. This feedback approach allows the system to maintain design flexibility while significantly reducing tracking time through adaptive phase correction.

Inventive Principle:
Principle #23Feedback

2Speed

If multiple phase adjustments are implemented, then tracking speed is improved, but system complexity increases

Engineering Contradiction:
Improvetracking speedVSAvoidsystem complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The patent implements dynamic phase adjustment capabilities where the system can switch between different phase states based on real-time conditions. By making the phase selection dynamic rather than fixed, the system achieves faster tracking speed while managing complexity through adaptive control rather than static multiple pathways.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent segments the phase adjustment process into discrete, manageable steps through a structured phase detector and control logic. This segmentation allows multiple phase adjustments to be implemented in a systematic way, improving tracking speed while keeping system complexity manageable through modular design elements.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS7778375B2Clock generator and data recovery circuit using the same
Publication Date: 2010.08.17 REALTEK SEMICON CORP
  • US7778375B2 patent drawing
  • US7778375B2 patent drawing
  • US7778375B2 patent drawing

AI summary

A clock generator and a data recovery circuit. The clock generator includes a voltage control oscillator (VCO) for generating a sampling clock and multi-phase clocks, a multiplexer for receiving the multi-phase clocks and selecting one of the multi-phase clocks to generate a selected clock according to a selection signal, a phase-frequency detector for receiving the selected clock and a reference clock and generating a phase-frequency error signal, a charge pump and loop filter for receiving the phase-frequency error signal and generating a control voltage, a phase detector for receiving the sampling clock and an input signal and generating a phase error signal, and a digital low-pass filter for receiving the phase error signal and generating the selection signal. The digital low-pass filter clears an accumulated phase error when it generates the selection signal to force the multiplexer to change the phase.