Clock Data Recovery with Phase-Monitored Equalizer Control
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Solution Overview
Problem
Existing clock data restoration devices face challenges in accurately restoring clock signals and data due to phase and frequency displacements, leading to inaccurate waveform correction and restoration.
Innovation Solution
A clock data restoration device comprising an equalizer section, a sampler section, a clock generation section, an equalizer control section, and a phase monitor section, which adjusts the level and phase of the clock signal based on detected values D(n) and DX(n) to minimize phase difference, and controls level adjustment based on phase monitoring to ensure accurate restoration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If phase and frequency control is performed on the clock signal to restore it, then clock signal restoration is achieved, but accurate data detection becomes impossible when phase and frequency are displaced by a large amount
Solution Approach 1:
The patent applies preliminary action by performing waveform correction through the equalizer section before data detection occurs. By pre-adjusting the signal waveform to an appropriate shape based on transmission loss characteristics, the system ensures that subsequent data detection can accurately capture data values even when clock phase and frequency are initially displaced. This preparatory waveform conditioning enables reliable operation of the phase-locked loop and data sampling circuits.
Solution Approach 2:
The patent implements feedback by continuously monitoring the detected data values and using them to adjust the equalizer control signal. The system detects data at multiple timing points, evaluates the quality of detection, and feeds this information back to modify the equalizer's waveform correction intensity. This closed-loop feedback mechanism dynamically optimizes the waveform correction to maintain accurate data detection under varying clock synchronization conditions.
2Manufacturing precision
If waveform correction intensity is adjusted based on detected data value, then suitable correction is achieved, but correction becomes inaccurate when data detection is inaccurate due to large phase and frequency displacement
Solution Approach 1:
The system performs preliminary waveform correction through the equalizer section before relying on data detection for control. By pre-shaping the waveform based on transmission characteristics and using the detected data values as reference points, the system establishes an accurate waveform foundation that enables subsequent data detection to be reliable even when clock synchronization is imperfect.
Solution Approach 2:
The patent applies partial action by performing waveform correction at specific critical points in the signal waveform rather than uniformly across the entire signal. The equalizer section selectively adjusts portions of the waveform that are most critical for data detection, focusing correction effort on the regions where accurate data sampling will occur, thereby achieving effective correction without requiring perfect data detection throughout the entire signal.
3Reliability
If data is detected at center time and transition time of bit period, then clock and data restoration is achieved, but restoration accuracy deteriorates when phase difference between clock signal and digital signal is large
Solution Approach 1:
The patent applies preliminary action by pre-adjusting the signal waveform through the equalizer section before data detection at critical timing points. By conditioning the waveform in advance based on transmission loss characteristics, the system ensures that when data is sampled at the center time and transition time of bit periods, the signal quality is sufficient for accurate detection even when clock phase and frequency are initially displaced.
Solution Approach 2:
The system implements feedback by using the data values detected at center time and transition time to continuously adjust the equalizer control signal. This feedback loop allows the system to evaluate the quality of detection at these critical sampling points and dynamically modify the waveform correction to maintain optimal detection accuracy, thereby improving overall restoration reliability under varying synchronization conditions.
Data Source
AI summary
The clock data restoration device 1 is a device which restores a clock signal and data on the basis of an input digital signal and comprises an equalizer section 10, a sampler section 20, a clock generation section 30, an equalizer control section 40, and a phase monitor section 50. As a result of the loop processing of the equalizer section 10, the sampler section 20, and the equalizer control section 40, a control of a level adjustment amount of the digital signal by the equalizer section 10 is carried out. However, the control is stopped by the phase monitor section 50 when the phase difference between the clock signal CK and the digital signal is greater than a predetermined value. As a result, a clock signal and data can be restored more accurately.