Clock Data Recovery Circuit for Quick Locking and Stable Bandwidth
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Solution Overview
Problem
In serial wired transmission systems, clock data recovery circuits face challenges with uncertain bandwidth and tracking jitters due to varying data transition densities, making it difficult to improve both bandwidth and tracking performance simultaneously.
Innovation Solution
A clock data recovery circuit with a phase detection circuit, adaptive tracking circuit, and clock control circuit that detects the position relation of clock edges and data edges to generate a tracking direction, allowing for quick locking and bandwidth stabilization by adjusting the sampling clock phase based on adaptive tracking directions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the bandwidth of the clock data recovery circuit is increased to improve tracking ability, then the tracking ability is improved, but the tracking jitters increase linearly
Solution Approach 1:
The patent implements dynamic bandwidth adjustment by switching between a first bandwidth (higher) during initial locking and a second bandwidth (lower) during normal operation. The bandwidth is dynamically adapted based on the locking state of the CDR circuit, allowing the system to optimize between tracking ability and jitter performance at different operational stages.
Solution Approach 2:
The patent employs periodic sampling of data edges at different phases within each clock period to detect phase lead/lag relationships. By periodically evaluating the phase relationship between clock edges and data edges, the system can determine tracking direction and adjust the sampling clock phase accordingly, enabling adaptive tracking without continuously increasing bandwidth.
2Speed
If the delay in the clock data recovery circuit is reduced to improve tracking response, then the tracking response is improved, but the system becomes more complex
Solution Approach 1:
The patent performs preliminary detection of the phase relationship between clock edges and data edges by sampling data at multiple phases within each clock period. This preliminary action allows the system to identify the optimal sampling phase in advance, reducing the delay required for tracking adjustments while maintaining manageable system complexity through structured phase sampling.
3Loss of time
If the bandwidth is increased to reduce locking time, then the locking speed is improved, but the tracking jitters increase
Solution Approach 1:
The patent dynamically adjusts the bandwidth of the CDR circuit based on the locking state. During the initial locking phase, a higher first bandwidth is used to quickly acquire lock and reduce locking time. Once locked, the system transitions to a lower second bandwidth to minimize tracking jitters during normal operation, thus resolving the trade-off between locking speed and jitter performance.
Data Source
AI summary
The present invention discloses a clock data recovery method having quick locking and bandwidth stabilizing mechanism used in a clock data recovery circuit. A relative position relation between a serial data and a sampling clock is detected by a phase detection circuit in an adaptive control period to generate a tracking direction. The tracking direction of a first clock period is directly outputted as an adaptive tracking direction by an adaptive tracking circuit. For each of the clock periods behind the first clock period, a previous tracking direction is replaced by a current tracking direction only when the current tracking direction exists and is different from the previous tracking direction of a previous clock period such that an actual tracking direction is generated when the adaptive tracking direction changes. The phase of the sampling clock is adjusted according to the actual tracking direction by a clock control circuit.