Clock Data Recovery Circuit for Synchronous Frequency-Phase Calibration
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Solution Overview
Problem
Existing clock and data recovery circuit modules in memory storage devices sequentially calibrate frequency and phase of clock signals, which is inefficient for systems prioritizing connection and initialization efficiency.
Innovation Solution
A clock and data recovery circuit module that includes detectors to detect frequency and phase differences, a clock signal generation circuit to generate signals based on these differences, and a phase adjustment circuit to adjust signals simultaneously, allowing for synchronous calibration of frequency and phase.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If frequency and phase calibration are performed sequentially, then each calibration can be completed accurately, but the overall calibration time is extended
Solution Approach 1:
The patent combines frequency calibration and phase calibration into a single synchronous operation. The first detector performs frequency calibration on the first clock signal while the second detector simultaneously performs phase calibration on the second clock signal, merging two sequential processes into one parallel process that reduces total calibration time while maintaining accuracy
Solution Approach 2:
The patent ensures continuous useful action by having both detectors operate simultaneously during calibration. The frequency calibration and phase calibration proceed in parallel without interruption, maximizing the utilization of calibration resources and minimizing idle time between calibration stages
2Reliability
If frequency calibration is performed first, then phase calibration can be performed, but the connection establishment efficiency is reduced
Solution Approach 1:
The patent prepares both calibration processes in advance by setting up the first and second detectors to operate simultaneously. The reference clock signal is prepared to be divided into multiple signals for parallel calibration, and the phase adjustment circuit is pre-configured to receive inputs from both detectors, enabling synchronous calibration that improves connection establishment efficiency
Solution Approach 2:
The patent introduces dynamic operation by allowing the system to switch between different calibration modes. The phase adjustment circuit can dynamically adjust the phase of clock signals based on real-time feedback from both detectors, enabling the system to adapt to different calibration requirements and improve overall efficiency
Data Source
AI summary
A clock and data recovery circuit module, a memory storage device and a signal calibration method are disclosed. The method comprises: receiving a reference clock signal and a first clock signal and detecting a first difference value between the reference clock signal and the first clock signal by a first detector; receiving a data signal and a second clock signal and detecting a second difference value between the data signal and the second clock signal by a second detector; generating a first clock signal and a second clock signal according to one of the first difference value and the second difference value; and adjusting one of the reference clock signal, the first clock signal and the second clock signal according to the second difference value.