Clock Recovery Training Circuit Offset Compensation
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Solution Overview
Problem
In high-speed communication systems, disabling the CDR circuit to reduce power consumption can lead to errors due to changes in power supply characteristics, causing mismatches between the clock and data components.
Innovation Solution
A circuit that determines a digital offset based on CDR codes at different times and applies this offset to the sampling clock when the CDR circuit is disabled, mitigating the effects of power supply changes on the sampling clock.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the CDR circuit is disabled to reduce power consumption, then power consumption is reduced, but bit errors increase due to sampling clock shifts caused by power supply characteristic changes
Solution Approach 1:
The system performs preliminary actions by capturing CDR codes at multiple time points (first time and second time after the first time) before disabling the CDR circuit. These preliminary captures allow the system to calculate a clock offset that compensates for future power supply changes, enabling the CDR circuit to be disabled while maintaining timing accuracy through pre-computed compensation values.
Solution Approach 2:
The system implements feedback by continuously monitoring CDR code changes over time and using these feedback signals to calculate clock offsets. The offset circuit receives feedback from the CDR circuit's output codes and dynamically computes compensation values that are applied to the sampling clock, creating a closed-loop system that maintains timing accuracy even when the CDR circuit is disabled.
2Use of energy by moving object
If the CDR circuit is disabled to reduce power consumption, then power consumption is reduced, but sampling clock accuracy deteriorates due to power supply characteristic changes
Solution Approach 1:
The system performs preliminary actions by capturing CDR codes at multiple time points (first time and second time after the first time) before disabling the CDR circuit. These preliminary captures allow the system to calculate a clock offset that compensates for future power supply changes, enabling the CDR circuit to be disabled while maintaining timing accuracy through pre-computed compensation values.
Solution Approach 2:
The system applies parameter changes by dynamically adjusting the sampling clock based on calculated clock offsets. The offset circuit modifies the sampling clock's timing parameters using the difference between CDR codes captured at different times, thereby compensating for power supply characteristic changes and maintaining sampling accuracy even when the CDR circuit is disabled.
3Use of energy by moving object
If the CDR circuit is disabled to reduce power consumption, then power consumption is reduced, but data interpretation accuracy decreases due to timing mismatches
Solution Approach 1:
The system introduces an intermediary mechanism - the offset circuit - that mediates between the disabled CDR circuit and the data sampling process. This intermediary calculates clock offsets based on CDR code changes and applies these offsets to the sampling clock, thereby bridging the gap created by the CDR circuit's disablement and maintaining data interpretation accuracy through indirect compensation.
Solution Approach 2:
The system performs preliminary actions by capturing CDR codes at multiple time points (first time and second time after the first time) before disabling the CDR circuit. These preliminary captures allow the system to calculate a clock offset that compensates for future power supply changes, enabling the CDR circuit to be disabled while maintaining timing accuracy through pre-computed compensation values.
Data Source
AI summary
In some examples, a method includes determining a first clock data recovery (CDR) code of a CDR circuit at a first time and determining a second CDR code of the CDR circuit at a second time after the first time. The method also includes generating, by a clock generator, a sampling clock for sampling a received data signal according to the first CDR code while the CDR circuit is active and determining, by an offset circuit, a clock offset based on the first CDR code and the second CDR code. Additionally, the method includes generating, by the clock generator, the sampling clock according to the clock offset responsive to disabling of the CDR circuit.