Clock Frequency Regulating Circuit with Buffer Occupancy Detection
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Solution Overview
Problem
Conventional retimers face issues with significant frequency variations in transmission clocks, leading to incorrect data reception and signal quality degradation during frequency synchronization, which affects the performance of back-end devices.
Innovation Solution
A clock frequency regulating circuit that includes a memory circuit, frequency detection circuit, and clock management unit, which adaptively adjusts the output clock frequency based on variations in the used storage space of the memory circuit, using a frequency detection result and optionally a water-level detection result to fine-tune the frequency adjustments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the transmission clock is aligned with the reception clock to reduce buffer size, then the circuit area is miniaturized, but significant frequency variation occurs during adjustment which prevents correct data reception
Solution Approach 1:
The patent applies preliminary action by pre-adjusting the transmission clock frequency to match the reception clock frequency before data transmission begins. The frequency adjustment is performed in advance based on detected frequency deviations, ensuring that the clock frequencies are synchronized before actual data transfer, thus avoiding frequency variation during critical data reception phases.
Solution Approach 2:
The patent implements dynamics by making the transmission clock frequency adjustable and adaptive. The system dynamically detects the frequency deviation between transmission and reception clocks, then automatically adjusts the transmission clock frequency to match the reception clock, creating a dynamic synchronization mechanism rather than a fixed frequency relationship.
2Quantity of substance
If the transmission clock is aligned with the reception clock, then the buffer size is reduced, but the output signal carries frequency fluctuation of the input signal which degrades signal quality
Solution Approach 1:
The patent extracts the frequency fluctuation problem by separating the clock synchronization function from the data transmission function. The system extracts only the necessary frequency adjustment information from the input signal to control the transmission clock, while preventing the propagation of harmful frequency fluctuations to the output data signal. This is achieved by using the detected frequency deviation solely for clock adjustment without allowing it to modulate the data signal.
Solution Approach 2:
The patent introduces an intermediary frequency adjustment mechanism that acts as a mediator between the reception clock and the transmission clock. This intermediary system detects frequency deviations and applies corrective adjustments to the transmission clock without allowing the original frequency fluctuations to directly affect the output signal, thus isolating the harmful fluctuations while maintaining synchronization.
Data Source
AI summary
A clock frequency regulating circuit includes a memory circuit, a frequency detection circuit, and a clock management unit (CMU). The memory circuit is configured to store data according to an input clock, and to output the data according to an output clock. The frequency detection circuit is coupled with the memory circuit, and configured to detect the variation in a used amount of a storage space of the memory circuit and accordingly generate a frequency detection result. The CMU is coupled with the frequency detection circuit, and configured to regulate the frequency of the output clock according to the frequency detection result.