Clock Resynchronization Using Reference-Clock Drift Correction

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Solution Overview

Problem

Clock drift during asynchronous communication leads to desynchronization between transmitter and receiver clocks, causing communication failures due to errors in the internal clock of the receiver, which affects the evaluation of data samples and results in cumulative errors that disrupt synchronization.

Innovation Solution

A system and method that utilize a sampling clock and a more precise reference clock to measure and correct clock drift by determining the difference in cycles over an observation window, allowing for the addition or subtraction of samples to maintain synchronization, thereby ensuring a desired data rate without increasing power consumption, area consumption, or design complexity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the receiver uses an internal sampling clock to evaluate data samples during asynchronous transmission, then the receiver can process incoming data, but clock drift causes cumulative errors that lead to loss of synchronization

Engineering Contradiction:
Improvedata processing capabilityVSAvoidsynchronization accuracy
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent implements a feedback mechanism where the system continuously measures the actual number of sampling clock cycles over a reference interval, compares it with the expected number of cycles, and uses this error information to adjust the sampling rate dynamically. This closed-loop control compensates for clock drift and maintains synchronization accuracy while preserving data processing capability.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The patent changes the sampling rate parameter dynamically based on measured clock drift. By adjusting the sampling frequency to match the actual transmitter rate, the system compensates for cumulative errors and maintains accurate symbol evaluation without sacrificing productivity.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If the receiver continuously monitors and corrects clock drift to maintain synchronization, then synchronization accuracy is improved, but system complexity and computational overhead increase

Engineering Contradiction:
Improvesynchronization accuracyVSAvoidsystem complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent performs clock drift measurement and correction at specific intervals rather than continuously. By measuring the sampling clock cycles over a fixed reference interval and applying corrections periodically, the system achieves adequate synchronization accuracy without the excessive complexity of continuous real-time adjustment.

Inventive Principle:
Principle #16Partial or excessive action

Solution Approach 2:

The patent introduces a reference clock or reference interval as an intermediary to measure and quantify the drift between transmitter and receiver clocks. This intermediary provides a stable basis for calculating the error and applying corrections, simplifying the overall synchronization mechanism while maintaining accuracy.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Measurement precision

If the receiver applies oversampling to improve data evaluation, then sampling accuracy is improved, but the cumulative clock error still causes desynchronization over time

Engineering Contradiction:
Improvedata sample evaluation accuracyVSAvoidlong-term synchronization
Core Design Contradiction:
Measurement precisionVSReliability

Solution Approach 1:

The patent combines oversampling with a feedback mechanism that measures the actual number of sampling cycles over a reference interval and uses this information to correct the sampling rate. This ensures that while oversampling provides short-term precision, the feedback loop prevents long-term drift and maintains synchronization reliability.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS11962677B2System and method for clock resynchronization
Publication Date: 2024.04.16 STMICROELECTRONICS SRL
  • US11962677B2 patent drawing
  • US11962677B2 patent drawing
  • US11962677B2 patent drawing

AI summary

A method of processing a data stream includes taking a first number of samples of the data stream using a sampling clock over a first observation window and storing a stored data stream including the first number of samples in a data buffer. A length of the first observation window is determined by a reference clock. A measured number of cycles of the sampling clock are determined from the first number of samples. An error between an expected number of cycles of the sampling clock and the measured number of cycles of the sampling clock in the observation window is measured. The stored data stream corresponding to the first observation window is updated to contain a second number of samples by correcting the first number of samples with the error.