Clock Signal Boost Circuit Low Voltage Operation
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Solution Overview
Problem
Conventional clock signal boost circuits fail to operate effectively when the power supply voltage (Vdd) is less than the absolute value of the threshold voltage of PMOS transistors.
Innovation Solution
Incorporation of depletion type NMOS transistors to charge a capacitor and boost the voltage, allowing the circuit to function even at low power supply voltages, along with a specific configuration of PMOS and NMOS transistors to manage clock signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional clock signal boost circuit is used, then the circuit structure is simple, but the circuit cannot operate when power supply voltage is less than the absolute value of PMOS transistor threshold voltage
Solution Approach 1:
The patent changes the transistor type from enhancement-type NMOS to depletion-type NMOS for specific positions in the circuit. This parameter change allows the circuit to operate at power supply voltages below the PMOS threshold voltage because depletion-type NMOS transistors have different electrical characteristics that enable conduction at lower voltages, thus resolving the operability issue while maintaining relatively simple circuit structure
Solution Approach 2:
The patent divides the circuit into specific functional segments, applying depletion-type NMOS transistors only where needed (in the voltage doubling path through capacitors) while using enhancement-type transistors elsewhere. This segmented approach allows the circuit to achieve low-voltage operability without making the entire circuit complex
2Reliability
If depletion type NMOS transistors are used to charge capacitor and boost voltage, then the circuit can operate at low power supply voltages, but the device complexity increases
Solution Approach 1:
The patent applies depletion-type NMOS transistors only in specific local positions where voltage boosting is required (connected to capacitors for voltage doubling), rather than throughout the entire circuit. This local application resolves the low-voltage operability issue while minimizing the increase in device complexity by limiting the special transistor types to only where they are functionally necessary
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables the clock signal boost circuit to operate and double the peak value of the clock signal, maintaining functionality at power supply voltages below the PMOS transistor threshold, while also optimizing for low current consumption and large load capacity in subsequent embodiments.
Implementation Method 1
the voltage of the node N42 rises to 2Vdd by capacitance coupling of the capacitor 403
Data Source
AI summary
A clock signal boost circuit includes a first NMOS transistor having a drain to a power terminal, a source to a first node, and a gate to a first terminal, a second NMOS transistor having a drain to the first node, a source to a GND, and a gate to a second terminal, a third NMOS transistor having a drain to the power terminal, a source to a second node, and a gate to the second terminal, a capacitor between the first node and the second node, a PMOS transistor having a source to the second node, a drain to an output terminal, and a gate to the second terminal, and a fourth NMOS transistor having a drain to the output terminal, a source to the GND, and a gate to the second terminal. The first and the third NMOS transistors are depletion type NMOS transistors.